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ehea: Allocate large enough skbs to avoid partial cacheline DMA writes

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The ehea adapter has a mode where it will avoid partial cacheline DMA
writes on receive by always padding packets to fall on a cacheline
boundary.

Unfortunately we currently aren't allocating enough space for a full
ethernet MTU packet to be rounded up, so this optimisation doesn't hit.

It's unfortunate that the next largest packet size exposed by the
hypervisor interface is 2kB, meaning our skb allocation comes out of a
4kB SLAB. However the performance increase due to this optimisation is
quite large and my TCP stream numbers increase from 900MB to 1000MB/sec.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Anton Blanchard 2011-10-14 05:31:04 +00:00 committed by David S. Miller
parent 076f203258
commit 945db2d4f4
1 changed files with 2 additions and 2 deletions
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4
drivers/net/ethernet/ibm/ehea/ehea.h
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@ -82,7 +82,7 @@
#define EHEA_SG_RQ3 0 #define EHEA_SG_RQ3 0
#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */ #define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
#define EHEA_RQ2_PKT_SIZE 1522 #define EHEA_RQ2_PKT_SIZE 2048
#define EHEA_L_PKT_SIZE 256 /* low latency */ #define EHEA_L_PKT_SIZE 256 /* low latency */
#define MAX_LRO_DESCRIPTORS 8 #define MAX_LRO_DESCRIPTORS 8
@ -93,7 +93,7 @@
#define EHEA_PD_ID 0xaabcdeff #define EHEA_PD_ID 0xaabcdeff
#define EHEA_RQ2_THRESHOLD 1 #define EHEA_RQ2_THRESHOLD 1
#define EHEA_RQ3_THRESHOLD 9 /* use RQ3 threshold of 1522 bytes */ #define EHEA_RQ3_THRESHOLD 4 /* use RQ3 threshold of 2048 bytes */
#define EHEA_SPEED_10G 10000 #define EHEA_SPEED_10G 10000
#define EHEA_SPEED_1G 1000 #define EHEA_SPEED_1G 1000