forked from Minki/linux
tg3: Add external loopback support to selftest
This patch adds external loopback support to tg3's ethtool selftest. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
28a4595786
commit
941ec90f35
@ -396,6 +396,7 @@ static const struct {
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{ "memory test (offline)" },
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{ "mac loopback test (offline)" },
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{ "phy loopback test (offline)" },
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{ "ext loopback test (offline)" },
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{ "interrupt test (offline)" },
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};
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@ -1680,6 +1681,36 @@ static void tg3_phy_fini(struct tg3 *tp)
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}
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}
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static int tg3_phy_set_extloopbk(struct tg3 *tp)
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{
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int err;
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u32 val;
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if (tp->phy_flags & TG3_PHYFLG_IS_FET)
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return 0;
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if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
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/* Cannot do read-modify-write on 5401 */
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err = tg3_phy_auxctl_write(tp,
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MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
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MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
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0x4c20);
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goto done;
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}
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err = tg3_phy_auxctl_read(tp,
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MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
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if (err)
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return err;
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val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
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err = tg3_phy_auxctl_write(tp,
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MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
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done:
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return err;
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}
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static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
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{
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u32 phytest;
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@ -6371,14 +6402,17 @@ static void tg3_mac_loopback(struct tg3 *tp, bool enable)
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udelay(40);
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}
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static void tg3_phy_lpbk_set(struct tg3 *tp, u32 speed)
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static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
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{
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u32 val, bmcr, mac_mode;
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u32 val, bmcr, mac_mode, ptest = 0;
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tg3_phy_toggle_apd(tp, false);
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tg3_phy_toggle_automdix(tp, 0);
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bmcr = BMCR_LOOPBACK | BMCR_FULLDPLX;
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if (extlpbk && tg3_phy_set_extloopbk(tp))
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return -EIO;
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bmcr = BMCR_FULLDPLX;
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switch (speed) {
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case SPEED_10:
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break;
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@ -6396,6 +6430,20 @@ static void tg3_phy_lpbk_set(struct tg3 *tp, u32 speed)
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}
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}
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if (extlpbk) {
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if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
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tg3_readphy(tp, MII_CTRL1000, &val);
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val |= CTL1000_AS_MASTER |
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CTL1000_ENABLE_MASTER;
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tg3_writephy(tp, MII_CTRL1000, val);
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} else {
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ptest = MII_TG3_FET_PTEST_TRIM_SEL |
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MII_TG3_FET_PTEST_TRIM_2;
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tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
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}
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} else
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bmcr |= BMCR_LOOPBACK;
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tg3_writephy(tp, MII_BMCR, bmcr);
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/* The write needs to be flushed for the FETs */
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@ -6406,7 +6454,7 @@ static void tg3_phy_lpbk_set(struct tg3 *tp, u32 speed)
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if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
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tg3_writephy(tp, MII_TG3_FET_PTEST,
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tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
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MII_TG3_FET_PTEST_FRC_TX_LINK |
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MII_TG3_FET_PTEST_FRC_TX_LOCK);
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@ -6443,6 +6491,8 @@ static void tg3_phy_lpbk_set(struct tg3 *tp, u32 speed)
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tw32(MAC_MODE, mac_mode);
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udelay(40);
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return 0;
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}
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static void tg3_set_loopback(struct net_device *dev, u32 features)
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@ -11542,7 +11592,7 @@ out:
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TG3_JMB_LOOPBACK_FAILED | \
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TG3_TSO_LOOPBACK_FAILED)
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static int tg3_test_loopback(struct tg3 *tp, u64 *data)
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static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
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{
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int err = -EIO;
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u32 eee_cap;
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@ -11553,6 +11603,8 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data)
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if (!netif_running(tp->dev)) {
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data[0] = TG3_LOOPBACK_FAILED;
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data[1] = TG3_LOOPBACK_FAILED;
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if (do_extlpbk)
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data[2] = TG3_LOOPBACK_FAILED;
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goto done;
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}
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@ -11560,6 +11612,8 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data)
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if (err) {
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data[0] = TG3_LOOPBACK_FAILED;
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data[1] = TG3_LOOPBACK_FAILED;
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if (do_extlpbk)
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data[2] = TG3_LOOPBACK_FAILED;
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goto done;
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}
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@ -11595,7 +11649,7 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data)
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!tg3_flag(tp, USE_PHYLIB)) {
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int i;
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tg3_phy_lpbk_set(tp, 0);
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tg3_phy_lpbk_set(tp, 0, false);
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/* Wait for link */
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for (i = 0; i < 100; i++) {
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@ -11613,12 +11667,31 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data)
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tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
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data[1] |= TG3_JMB_LOOPBACK_FAILED;
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if (do_extlpbk) {
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tg3_phy_lpbk_set(tp, 0, true);
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/* All link indications report up, but the hardware
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* isn't really ready for about 20 msec. Double it
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* to be sure.
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*/
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mdelay(40);
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if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
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data[2] |= TG3_STD_LOOPBACK_FAILED;
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if (tg3_flag(tp, TSO_CAPABLE) &&
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tg3_run_loopback(tp, ETH_FRAME_LEN, true))
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data[2] |= TG3_TSO_LOOPBACK_FAILED;
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if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
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tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
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data[2] |= TG3_JMB_LOOPBACK_FAILED;
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}
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/* Re-enable gphy autopowerdown. */
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if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
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tg3_phy_toggle_apd(tp, true);
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}
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err = (data[0] | data[1]) ? -EIO : 0;
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err = (data[0] | data[1] | data[2]) ? -EIO : 0;
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done:
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tp->phy_flags |= eee_cap;
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@ -11630,6 +11703,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
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u64 *data)
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{
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struct tg3 *tp = netdev_priv(dev);
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bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
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if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
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tg3_power_up(tp)) {
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@ -11644,7 +11718,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
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etest->flags |= ETH_TEST_FL_FAILED;
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data[0] = 1;
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}
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if (tg3_test_link(tp) != 0) {
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if (!doextlpbk && tg3_test_link(tp)) {
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etest->flags |= ETH_TEST_FL_FAILED;
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data[1] = 1;
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}
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@ -11680,14 +11754,17 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
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data[3] = 1;
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}
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if (tg3_test_loopback(tp, &data[4]))
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if (doextlpbk)
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etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
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if (tg3_test_loopback(tp, &data[4], doextlpbk))
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etest->flags |= ETH_TEST_FL_FAILED;
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tg3_full_unlock(tp);
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if (tg3_test_interrupt(tp) != 0) {
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etest->flags |= ETH_TEST_FL_FAILED;
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data[6] = 1;
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data[7] = 1;
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}
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tg3_full_lock(tp, 0);
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@ -2197,6 +2197,7 @@
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#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
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#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
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#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
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#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
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#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
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#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
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@ -2262,6 +2263,8 @@
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/* Fast Ethernet Tranceiver definitions */
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#define MII_TG3_FET_PTEST 0x17
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#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
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#define MII_TG3_FET_PTEST_TRIM_2 0x0002
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#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
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#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
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