Merge tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm
Pull drm msm updates from Dave Airlie:
"This tree has been in next for a couple of weeks, but Rob missed an
arm32 build issue, so I was awaiting the tree with a patch reverted.
- new gpu support: a405, a640, a650
- dpu: color processing support
- mdp5: support for msm8x36 (the thing with a405)
- some prep work for per-context pagetables (ie the part that does
not depend on in-flight iommu patches)
- last but not least, UABI update for submit ioctl to support syncobj
(from Bas)"
* tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm: (30 commits)
Revert "drm/msm/dpu: add support for clk and bw scaling for display"
drm/msm/a6xx: skip HFI set freq if GMU is powered down
drm/msm: Update the MMU helper function APIs
drm/msm: Refactor address space initialization
drm/msm: Attach the IOMMU device during initialization
drm/msm/dpu: dpu_setup_dspp_pcc() can be static
drm/msm/a6xx: a6xx_hfi_send_start() can be static
drm/msm/a4xx: add a405_registers for a405 device
drm/msm/a4xx: add adreno a405 support
drm/msm/a6xx: update a6xx_hw_init for A640 and A650
drm/msm/a6xx: enable GMU log
drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650
drm/msm/a6xx: A640/A650 GMU firmware path
drm/msm/a6xx: HFI v2 for A640 and A650
drm/msm/a6xx: add A640/A650 to gpulist
drm/msm/a6xx: use msm_gem for GMU memory objects
drm/msm: add internal MSM_BO_MAP_PRIV flag
drm/msm: add msm_gem_get_and_pin_iova_range
drm/msm: Check for powered down HW in the devfreq callbacks
drm/msm/dpu: update bandwidth threshold check
...
This commit is contained in:
@@ -217,13 +217,28 @@ struct drm_msm_gem_submit_bo {
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#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
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#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
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#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
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#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
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#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
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#define MSM_SUBMIT_FLAGS ( \
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MSM_SUBMIT_NO_IMPLICIT | \
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MSM_SUBMIT_FENCE_FD_IN | \
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MSM_SUBMIT_FENCE_FD_OUT | \
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MSM_SUBMIT_SUDO | \
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MSM_SUBMIT_SYNCOBJ_IN | \
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MSM_SUBMIT_SYNCOBJ_OUT | \
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0)
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#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
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#define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
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MSM_SUBMIT_SYNCOBJ_RESET | \
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0)
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struct drm_msm_gem_submit_syncobj {
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__u32 handle; /* in, syncobj handle. */
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__u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
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__u64 point; /* in, timepoint for timeline syncobjs. */
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};
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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@@ -236,7 +251,14 @@ struct drm_msm_gem_submit {
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__u64 bos; /* in, ptr to array of submit_bo's */
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__u64 cmds; /* in, ptr to array of submit_cmd's */
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__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
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__u32 queueid; /* in, submitqueue id */
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__u32 queueid; /* in, submitqueue id */
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__u64 in_syncobjs; /* in, ptr to to array of drm_msm_gem_submit_syncobj */
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__u64 out_syncobjs; /* in, ptr to to array of drm_msm_gem_submit_syncobj */
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__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
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__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
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__u32 syncobj_stride; /* in, stride of syncobj arrays. */
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__u32 pad; /*in, reserved for future use, always 0. */
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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