- mt7623: add mt7623n and mt7623a plattform
- add mt7623 based reference boards - mt7623: add usb3, ethernet, cpufreq, - Add banana-pi board - add mt6323 pmic - mt2701: add larb-id property to smi larb -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlmVfAMXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00NzChAAnj/93phTJunguMQlmiLopPFq a6ojH7ETUom+cajkm+vrYoJgfltYi4ghVfJhjlqsUNIjKfdT8GcfH9Ic0ceOgJIJ d1ss1D5SVuvtDshhS4Ja6NP5oBXLjpvf3Mf5AIcOMkWw0d+dmPk4wJQ4WnyaWUdz 8RzN4i9JNdcvTuFLpq99gdJerS/sQ1oXAd1QzIcvKr4YFzdxE/RrBLOBVHxP6OpD N8/hIb2bVsS1vfaPsI/UeN19jpxTxMrttRYCt1PBVcwribifG+C+jQg9kJXnewaj J/3FoXQBtLwoSDDxZq/p5woDZhfDnsgAo0szmHbxVBdrKZWPvWxekneoc8uYnFI4 i9NVtpnPSVGzCxuHrEwOVWuS4okKgwEho6tqot8P7MzjwQ4v0ms9S3m/bJz55ZIf QCqnPHb4LMnwdkHhgI4oFgz5YjsC3pjsxcsEbC3VNyFx4qfbq8u9ZcjQWOUxPitF R+tlJVp0TJOJkOg2ZMAqaF0BYM7NeXmC2owKSM649k6/n/Mw44tLm8SGPTBPzq6n Iyxlf3vir+eGKhVfgOLhHd/3Yre1qPxcZ5KwwEJHo8f3alWUE4fCORtu2TWnaxhp 5dkt7j8QlNAoti7apo8eiN4srWSv2GZJNeR5gth0X9KNFzyKt/gIsIRQCf38UqbF NwMfgKXfcXGI6DOt7To= =yAoq -----END PGP SIGNATURE----- Merge tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek into next/dt - mt7623: add mt7623n and mt7623a plattform - add mt7623 based reference boards - mt7623: add usb3, ethernet, cpufreq, - Add banana-pi board - add mt6323 pmic - mt2701: add larb-id property to smi larb * tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek: arm: dts: mt7623: cleanup binding file arm: dts: mt7623: Add SD-card and EMMC to bananapi-r2 arm: dts: mediatek: add larbid property for larb arm: dts: mt7623: fix mmc interrupt assignment arm: dts: mt2701: Add usb3 device nodes arm: dts: mt2701: Add ethernet device node arm: dts: mt7623: add clock-frequency to CPU nodes arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board arm: dts: mt7623: enable the nand device on the mt7623n nand rfb arm: dts: mt7623: enable the usb device on the mt7623n rfb arm: dts: mt7623: cleanup the mt7623n rfb uart nodes arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi arm: dts: mt7623: add mt6323.dtsi file dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC Platform dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards arm: dts: mt7623: fixup binding violation missing reset in ethernet node dt-bindings: net: mediatek: update documentation for reset signals Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
940bf1d6f7
@ -1,7 +1,6 @@
|
|||||||
MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
|
MediaTek SoC based Platforms Device Tree Bindings
|
||||||
|
|
||||||
Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
|
Boards with a MediaTek SoC shall have the following property:
|
||||||
following property:
|
|
||||||
|
|
||||||
Required root node property:
|
Required root node property:
|
||||||
|
|
||||||
@ -14,7 +13,8 @@ compatible: Must contain one of
|
|||||||
"mediatek,mt6795"
|
"mediatek,mt6795"
|
||||||
"mediatek,mt6797"
|
"mediatek,mt6797"
|
||||||
"mediatek,mt7622"
|
"mediatek,mt7622"
|
||||||
"mediatek,mt7623"
|
"mediatek,mt7623" which is referred to MT7623N SoC
|
||||||
|
"mediatek,mt7623a"
|
||||||
"mediatek,mt8127"
|
"mediatek,mt8127"
|
||||||
"mediatek,mt8135"
|
"mediatek,mt8135"
|
||||||
"mediatek,mt8173"
|
"mediatek,mt8173"
|
||||||
@ -46,9 +46,11 @@ Supported boards:
|
|||||||
- Reference board variant 1 for MT7622:
|
- Reference board variant 1 for MT7622:
|
||||||
Required root node properties:
|
Required root node properties:
|
||||||
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
|
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
|
||||||
- Evaluation board for MT7623:
|
- Reference board for MT7623n with NAND:
|
||||||
Required root node properties:
|
Required root node properties:
|
||||||
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
|
||||||
|
- Bananapi BPI-R2 board:
|
||||||
|
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
|
||||||
- MTK mt8127 tablet moose EVB:
|
- MTK mt8127 tablet moose EVB:
|
||||||
Required root node properties:
|
Required root node properties:
|
||||||
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
|
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
|
||||||
|
|||||||
@ -15,8 +15,10 @@ Required properties:
|
|||||||
- clock-names: the names of the clock listed in the clocks property. These are
|
- clock-names: the names of the clock listed in the clocks property. These are
|
||||||
"ethif", "esw", "gp2", "gp1"
|
"ethif", "esw", "gp2", "gp1"
|
||||||
- power-domains: phandle to the power domain that the ethernet is part of
|
- power-domains: phandle to the power domain that the ethernet is part of
|
||||||
- resets: Should contain a phandle to the ethsys reset signal
|
- resets: Should contain phandles to the ethsys reset signals
|
||||||
- reset-names: Should contain the reset signal name "eth"
|
- reset-names: Should contain the names of reset signal listed in the resets
|
||||||
|
property
|
||||||
|
These are "fe", "gmac" and "ppe"
|
||||||
- mediatek,ethsys: phandle to the syscon node that handles the port setup
|
- mediatek,ethsys: phandle to the syscon node that handles the port setup
|
||||||
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
|
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
|
||||||
and driver current
|
and driver current
|
||||||
|
|||||||
@ -1058,7 +1058,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
|||||||
mt6580-evbp1.dtb \
|
mt6580-evbp1.dtb \
|
||||||
mt6589-aquaris5.dtb \
|
mt6589-aquaris5.dtb \
|
||||||
mt6592-evb.dtb \
|
mt6592-evb.dtb \
|
||||||
mt7623-evb.dtb \
|
mt7623n-rfb-nand.dtb \
|
||||||
|
mt7623n-bananapi-bpi-r2.dtb \
|
||||||
mt8127-moose.dtb \
|
mt8127-moose.dtb \
|
||||||
mt8135-evbp1.dtb
|
mt8135-evbp1.dtb
|
||||||
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
|
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
|
||||||
|
|||||||
@ -13,6 +13,7 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <dt-bindings/clock/mt2701-clk.h>
|
#include <dt-bindings/clock/mt2701-clk.h>
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
#include <dt-bindings/power/mt2701-power.h>
|
#include <dt-bindings/power/mt2701-power.h>
|
||||||
#include <dt-bindings/interrupt-controller/irq.h>
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
@ -533,6 +534,7 @@
|
|||||||
compatible = "mediatek,mt2701-smi-larb";
|
compatible = "mediatek,mt2701-smi-larb";
|
||||||
reg = <0 0x14010000 0 0x1000>;
|
reg = <0 0x14010000 0 0x1000>;
|
||||||
mediatek,smi = <&smi_common>;
|
mediatek,smi = <&smi_common>;
|
||||||
|
mediatek,larb-id = <0>;
|
||||||
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
||||||
<&mmsys CLK_MM_SMI_LARB0>;
|
<&mmsys CLK_MM_SMI_LARB0>;
|
||||||
clock-names = "apb", "smi";
|
clock-names = "apb", "smi";
|
||||||
@ -549,6 +551,7 @@
|
|||||||
compatible = "mediatek,mt2701-smi-larb";
|
compatible = "mediatek,mt2701-smi-larb";
|
||||||
reg = <0 0x15001000 0 0x1000>;
|
reg = <0 0x15001000 0 0x1000>;
|
||||||
mediatek,smi = <&smi_common>;
|
mediatek,smi = <&smi_common>;
|
||||||
|
mediatek,larb-id = <2>;
|
||||||
clocks = <&imgsys CLK_IMG_SMI_COMM>,
|
clocks = <&imgsys CLK_IMG_SMI_COMM>,
|
||||||
<&imgsys CLK_IMG_SMI_COMM>;
|
<&imgsys CLK_IMG_SMI_COMM>;
|
||||||
clock-names = "apb", "smi";
|
clock-names = "apb", "smi";
|
||||||
@ -579,6 +582,7 @@
|
|||||||
compatible = "mediatek,mt2701-smi-larb";
|
compatible = "mediatek,mt2701-smi-larb";
|
||||||
reg = <0 0x16010000 0 0x1000>;
|
reg = <0 0x16010000 0 0x1000>;
|
||||||
mediatek,smi = <&smi_common>;
|
mediatek,smi = <&smi_common>;
|
||||||
|
mediatek,larb-id = <1>;
|
||||||
clocks = <&vdecsys CLK_VDEC_CKGEN>,
|
clocks = <&vdecsys CLK_VDEC_CKGEN>,
|
||||||
<&vdecsys CLK_VDEC_LARB>;
|
<&vdecsys CLK_VDEC_LARB>;
|
||||||
clock-names = "apb", "smi";
|
clock-names = "apb", "smi";
|
||||||
@ -591,12 +595,114 @@
|
|||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb0: usb@1a1c0000 {
|
||||||
|
compatible = "mediatek,mt8173-xhci";
|
||||||
|
reg = <0 0x1a1c0000 0 0x1000>,
|
||||||
|
<0 0x1a1c4700 0 0x0100>;
|
||||||
|
reg-names = "mac", "ippc";
|
||||||
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
|
||||||
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
||||||
|
clock-names = "sys_ck", "ref_ck";
|
||||||
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||||
|
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
u3phy0: usb-phy@1a1c4000 {
|
||||||
|
compatible = "mediatek,mt2701-u3phy";
|
||||||
|
reg = <0 0x1a1c4000 0 0x0700>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
u2port0: usb-phy@1a1c4800 {
|
||||||
|
reg = <0 0x1a1c4800 0 0x0100>;
|
||||||
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
u3port0: usb-phy@1a1c4900 {
|
||||||
|
reg = <0 0x1a1c4900 0 0x0700>;
|
||||||
|
clocks = <&clk26m>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usb1: usb@1a240000 {
|
||||||
|
compatible = "mediatek,mt8173-xhci";
|
||||||
|
reg = <0 0x1a240000 0 0x1000>,
|
||||||
|
<0 0x1a244700 0 0x0100>;
|
||||||
|
reg-names = "mac", "ippc";
|
||||||
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
|
||||||
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
||||||
|
clock-names = "sys_ck", "ref_ck";
|
||||||
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
||||||
|
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
u3phy1: usb-phy@1a244000 {
|
||||||
|
compatible = "mediatek,mt2701-u3phy";
|
||||||
|
reg = <0 0x1a244000 0 0x0700>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
u2port1: usb-phy@1a244800 {
|
||||||
|
reg = <0 0x1a244800 0 0x0100>;
|
||||||
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
u3port1: usb-phy@1a244900 {
|
||||||
|
reg = <0 0x1a244900 0 0x0700>;
|
||||||
|
clocks = <&clk26m>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
ethsys: syscon@1b000000 {
|
ethsys: syscon@1b000000 {
|
||||||
compatible = "mediatek,mt2701-ethsys", "syscon";
|
compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||||
reg = <0 0x1b000000 0 0x1000>;
|
reg = <0 0x1b000000 0 0x1000>;
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
eth: ethernet@1b100000 {
|
||||||
|
compatible = "mediatek,mt2701-eth", "syscon";
|
||||||
|
reg = <0 0x1b100000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||||
|
<ðsys CLK_ETHSYS_ESW>,
|
||||||
|
<ðsys CLK_ETHSYS_GP1>,
|
||||||
|
<ðsys CLK_ETHSYS_GP2>,
|
||||||
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
||||||
|
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
||||||
|
resets = <ðsys MT2701_ETHSYS_FE_RST>,
|
||||||
|
<ðsys MT2701_ETHSYS_GMAC_RST>,
|
||||||
|
<ðsys MT2701_ETHSYS_PPE_RST>;
|
||||||
|
reset-names = "fe", "gmac", "ppe";
|
||||||
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||||
|
mediatek,ethsys = <ðsys>;
|
||||||
|
mediatek,pctl = <&syscfg_pctl_a>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
bdpsys: syscon@1c000000 {
|
bdpsys: syscon@1c000000 {
|
||||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||||
reg = <0 0x1c000000 0 0x1000>;
|
reg = <0 0x1c000000 0 0x1000>;
|
||||||
|
|||||||
241
arch/arm/boot/dts/mt6323.dtsi
Normal file
241
arch/arm/boot/dts/mt6323.dtsi
Normal file
@ -0,0 +1,241 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017 MediaTek Inc.
|
||||||
|
* Author: John Crispin <john@phrozen.org>
|
||||||
|
* Sean Wang <sean.wang@mediatek.com>
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
&pwrap {
|
||||||
|
pmic: mt6323 {
|
||||||
|
compatible = "mediatek,mt6323";
|
||||||
|
interrupt-parent = <&pio>;
|
||||||
|
interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
|
mt6323regulator: mt6323regulator{
|
||||||
|
compatible = "mediatek,mt6323-regulator";
|
||||||
|
|
||||||
|
mt6323_vproc_reg: buck_vproc{
|
||||||
|
regulator-name = "vproc";
|
||||||
|
regulator-min-microvolt = < 700000>;
|
||||||
|
regulator-max-microvolt = <1350000>;
|
||||||
|
regulator-ramp-delay = <12500>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vsys_reg: buck_vsys{
|
||||||
|
regulator-name = "vsys";
|
||||||
|
regulator-min-microvolt = <1400000>;
|
||||||
|
regulator-max-microvolt = <2987500>;
|
||||||
|
regulator-ramp-delay = <25000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vpa_reg: buck_vpa{
|
||||||
|
regulator-name = "vpa";
|
||||||
|
regulator-min-microvolt = < 500000>;
|
||||||
|
regulator-max-microvolt = <3650000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vtcxo_reg: ldo_vtcxo{
|
||||||
|
regulator-name = "vtcxo";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-enable-ramp-delay = <90>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcn28_reg: ldo_vcn28{
|
||||||
|
regulator-name = "vcn28";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-enable-ramp-delay = <185>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcn33_bt_reg: ldo_vcn33_bt{
|
||||||
|
regulator-name = "vcn33_bt";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3600000>;
|
||||||
|
regulator-enable-ramp-delay = <185>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
|
||||||
|
regulator-name = "vcn33_wifi";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3600000>;
|
||||||
|
regulator-enable-ramp-delay = <185>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_va_reg: ldo_va{
|
||||||
|
regulator-name = "va";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcama_reg: ldo_vcama{
|
||||||
|
regulator-name = "vcama";
|
||||||
|
regulator-min-microvolt = <1500000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vio28_reg: ldo_vio28{
|
||||||
|
regulator-name = "vio28";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vusb_reg: ldo_vusb{
|
||||||
|
regulator-name = "vusb";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vmc_reg: ldo_vmc{
|
||||||
|
regulator-name = "vmc";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <36>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vmch_reg: ldo_vmch{
|
||||||
|
regulator-name = "vmch";
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <36>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vemc3v3_reg: ldo_vemc3v3{
|
||||||
|
regulator-name = "vemc3v3";
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <36>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vgp1_reg: ldo_vgp1{
|
||||||
|
regulator-name = "vgp1";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vgp2_reg: ldo_vgp2{
|
||||||
|
regulator-name = "vgp2";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vgp3_reg: ldo_vgp3{
|
||||||
|
regulator-name = "vgp3";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcn18_reg: ldo_vcn18{
|
||||||
|
regulator-name = "vcn18";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vsim1_reg: ldo_vsim1{
|
||||||
|
regulator-name = "vsim1";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vsim2_reg: ldo_vsim2{
|
||||||
|
regulator-name = "vsim2";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vrtc_reg: ldo_vrtc{
|
||||||
|
regulator-name = "vrtc";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcamaf_reg: ldo_vcamaf{
|
||||||
|
regulator-name = "vcamaf";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vibr_reg: ldo_vibr{
|
||||||
|
regulator-name = "vibr";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-enable-ramp-delay = <36>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vrf18_reg: ldo_vrf18{
|
||||||
|
regulator-name = "vrf18";
|
||||||
|
regulator-min-microvolt = <1825000>;
|
||||||
|
regulator-max-microvolt = <1825000>;
|
||||||
|
regulator-enable-ramp-delay = <187>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vm_reg: ldo_vm{
|
||||||
|
regulator-name = "vm";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vio18_reg: ldo_vio18{
|
||||||
|
regulator-name = "vio18";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcamd_reg: ldo_vcamd{
|
||||||
|
regulator-name = "vcamd";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mt6323_vcamio_reg: ldo_vcamio{
|
||||||
|
regulator-name = "vcamio";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-enable-ramp-delay = <216>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
@ -1,33 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2016 MediaTek Inc.
|
|
||||||
* Author: John Crispin <john@phrozen.org>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/dts-v1/;
|
|
||||||
#include "mt7623.dtsi"
|
|
||||||
|
|
||||||
/ {
|
|
||||||
model = "MediaTek MT7623 evaluation board";
|
|
||||||
compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
|
||||||
|
|
||||||
chosen {
|
|
||||||
stdout-path = &uart2;
|
|
||||||
};
|
|
||||||
|
|
||||||
memory {
|
|
||||||
reg = <0 0x80000000 0 0x40000000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
&uart2 {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
@ -21,36 +21,99 @@
|
|||||||
#include <dt-bindings/gpio/gpio.h>
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
#include <dt-bindings/phy/phy.h>
|
#include <dt-bindings/phy/phy.h>
|
||||||
#include <dt-bindings/reset/mt2701-resets.h>
|
#include <dt-bindings/reset/mt2701-resets.h>
|
||||||
|
#include <dt-bindings/thermal/thermal.h>
|
||||||
#include "skeleton64.dtsi"
|
#include "skeleton64.dtsi"
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "mediatek,mt7623";
|
compatible = "mediatek,mt7623";
|
||||||
interrupt-parent = <&sysirq>;
|
interrupt-parent = <&sysirq>;
|
||||||
|
|
||||||
|
cpu_opp_table: opp_table {
|
||||||
|
compatible = "operating-points-v2";
|
||||||
|
opp-shared;
|
||||||
|
|
||||||
|
opp-98000000 {
|
||||||
|
opp-hz = /bits/ 64 <98000000>;
|
||||||
|
opp-microvolt = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-198000000 {
|
||||||
|
opp-hz = /bits/ 64 <198000000>;
|
||||||
|
opp-microvolt = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-398000000 {
|
||||||
|
opp-hz = /bits/ 64 <398000000>;
|
||||||
|
opp-microvolt = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-598000000 {
|
||||||
|
opp-hz = /bits/ 64 <598000000>;
|
||||||
|
opp-microvolt = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-747500000 {
|
||||||
|
opp-hz = /bits/ 64 <747500000>;
|
||||||
|
opp-microvolt = <1050000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-1040000000 {
|
||||||
|
opp-hz = /bits/ 64 <1040000000>;
|
||||||
|
opp-microvolt = <1150000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-1196000000 {
|
||||||
|
opp-hz = /bits/ 64 <1196000000>;
|
||||||
|
opp-microvolt = <1200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp-1300000000 {
|
||||||
|
opp-hz = /bits/ 64 <1300000000>;
|
||||||
|
opp-microvolt = <1300000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
enable-method = "mediatek,mt6589-smp";
|
enable-method = "mediatek,mt6589-smp";
|
||||||
|
|
||||||
cpu@0 {
|
cpu0: cpu@0 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a7";
|
compatible = "arm,cortex-a7";
|
||||||
reg = <0x0>;
|
reg = <0x0>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_CPUSEL>,
|
||||||
|
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||||
|
clock-names = "cpu", "intermediate";
|
||||||
|
operating-points-v2 = <&cpu_opp_table>;
|
||||||
|
#cooling-cells = <2>;
|
||||||
|
cooling-min-level = <0>;
|
||||||
|
cooling-max-level = <7>;
|
||||||
|
clock-frequency = <1300000000>;
|
||||||
};
|
};
|
||||||
cpu@1 {
|
|
||||||
|
cpu1: cpu@1 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a7";
|
compatible = "arm,cortex-a7";
|
||||||
reg = <0x1>;
|
reg = <0x1>;
|
||||||
|
operating-points-v2 = <&cpu_opp_table>;
|
||||||
|
clock-frequency = <1300000000>;
|
||||||
};
|
};
|
||||||
cpu@2 {
|
|
||||||
|
cpu2: cpu@2 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a7";
|
compatible = "arm,cortex-a7";
|
||||||
reg = <0x2>;
|
reg = <0x2>;
|
||||||
|
operating-points-v2 = <&cpu_opp_table>;
|
||||||
|
clock-frequency = <1300000000>;
|
||||||
};
|
};
|
||||||
cpu@3 {
|
|
||||||
|
cpu3: cpu@3 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a7";
|
compatible = "arm,cortex-a7";
|
||||||
reg = <0x3>;
|
reg = <0x3>;
|
||||||
|
operating-points-v2 = <&cpu_opp_table>;
|
||||||
|
clock-frequency = <1300000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -74,6 +137,58 @@
|
|||||||
clock-output-names = "clk26m";
|
clock-output-names = "clk26m";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
thermal-zones {
|
||||||
|
cpu_thermal: cpu_thermal {
|
||||||
|
polling-delay-passive = <1000>;
|
||||||
|
polling-delay = <1000>;
|
||||||
|
|
||||||
|
thermal-sensors = <&thermal 0>;
|
||||||
|
|
||||||
|
trips {
|
||||||
|
cpu_passive: cpu_passive {
|
||||||
|
temperature = <47000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "passive";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_active: cpu_active {
|
||||||
|
temperature = <67000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_hot: cpu_hot {
|
||||||
|
temperature = <87000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "hot";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_crit {
|
||||||
|
temperature = <107000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "critical";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
map0 {
|
||||||
|
trip = <&cpu_passive>;
|
||||||
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||||
|
};
|
||||||
|
|
||||||
|
map1 {
|
||||||
|
trip = <&cpu_active>;
|
||||||
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||||
|
};
|
||||||
|
|
||||||
|
map2 {
|
||||||
|
trip = <&cpu_hot>;
|
||||||
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
timer {
|
timer {
|
||||||
compatible = "arm,armv7-timer";
|
compatible = "arm,armv7-timer";
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
@ -172,7 +287,7 @@
|
|||||||
clock-names = "spi", "wrap";
|
clock-names = "spi", "wrap";
|
||||||
};
|
};
|
||||||
|
|
||||||
cir: cir@0x10013000 {
|
cir: cir@10013000 {
|
||||||
compatible = "mediatek,mt7623-cir";
|
compatible = "mediatek,mt7623-cir";
|
||||||
reg = <0 0x10013000 0 0x1000>;
|
reg = <0 0x10013000 0 0x1000>;
|
||||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
||||||
@ -193,7 +308,7 @@
|
|||||||
efuse: efuse@10206000 {
|
efuse: efuse@10206000 {
|
||||||
compatible = "mediatek,mt7623-efuse",
|
compatible = "mediatek,mt7623-efuse",
|
||||||
"mediatek,mt8173-efuse";
|
"mediatek,mt8173-efuse";
|
||||||
reg = <0 0x10206000 0 0x1000>;
|
reg = <0 0x10206000 0 0x1000>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
thermal_calibration_data: calib@424 {
|
thermal_calibration_data: calib@424 {
|
||||||
@ -371,6 +486,31 @@
|
|||||||
nvmem-cell-names = "calibration-data";
|
nvmem-cell-names = "calibration-data";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
nandc: nfi@1100d000 {
|
||||||
|
compatible = "mediatek,mt7623-nfc",
|
||||||
|
"mediatek,mt2701-nfc";
|
||||||
|
reg = <0 0x1100d000 0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
||||||
|
clocks = <&pericfg CLK_PERI_NFI>,
|
||||||
|
<&pericfg CLK_PERI_NFI_PAD>;
|
||||||
|
clock-names = "nfi_clk", "pad_clk";
|
||||||
|
status = "disabled";
|
||||||
|
ecc-engine = <&bch>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
bch: ecc@1100e000 {
|
||||||
|
compatible = "mediatek,mt7623-ecc",
|
||||||
|
"mediatek,mt2701-ecc";
|
||||||
|
reg = <0 0x1100e000 0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
||||||
|
clock-names = "nfiecc_clk";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
spi1: spi@11016000 {
|
spi1: spi@11016000 {
|
||||||
compatible = "mediatek,mt7623-spi",
|
compatible = "mediatek,mt7623-spi",
|
||||||
"mediatek,mt2701-spi";
|
"mediatek,mt2701-spi";
|
||||||
@ -399,31 +539,6 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
nandc: nfi@1100d000 {
|
|
||||||
compatible = "mediatek,mt7623-nfc",
|
|
||||||
"mediatek,mt2701-nfc";
|
|
||||||
reg = <0 0x1100d000 0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
|
||||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
||||||
clocks = <&pericfg CLK_PERI_NFI>,
|
|
||||||
<&pericfg CLK_PERI_NFI_PAD>;
|
|
||||||
clock-names = "nfi_clk", "pad_clk";
|
|
||||||
status = "disabled";
|
|
||||||
ecc-engine = <&bch>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
bch: ecc@1100e000 {
|
|
||||||
compatible = "mediatek,mt7623-ecc",
|
|
||||||
"mediatek,mt2701-ecc";
|
|
||||||
reg = <0 0x1100e000 0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
|
||||||
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
|
||||||
clock-names = "nfiecc_clk";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
afe: audio-controller@11220000 {
|
afe: audio-controller@11220000 {
|
||||||
compatible = "mediatek,mt7623-audio",
|
compatible = "mediatek,mt7623-audio",
|
||||||
"mediatek,mt2701-audio";
|
"mediatek,mt2701-audio";
|
||||||
@ -538,13 +653,22 @@
|
|||||||
compatible = "mediatek,mt7623-mmc",
|
compatible = "mediatek,mt7623-mmc",
|
||||||
"mediatek,mt8135-mmc";
|
"mediatek,mt8135-mmc";
|
||||||
reg = <0 0x11240000 0 0x1000>;
|
reg = <0 0x11240000 0 0x1000>;
|
||||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
|
||||||
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
||||||
<&topckgen CLK_TOP_MSDC30_1_SEL>;
|
<&topckgen CLK_TOP_MSDC30_1_SEL>;
|
||||||
clock-names = "source", "hclk";
|
clock-names = "source", "hclk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
hifsys: syscon@1a000000 {
|
||||||
|
compatible = "mediatek,mt7623-hifsys",
|
||||||
|
"mediatek,mt2701-hifsys",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x1a000000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
usb1: usb@1a1c0000 {
|
usb1: usb@1a1c0000 {
|
||||||
compatible = "mediatek,mt7623-xhci",
|
compatible = "mediatek,mt7623-xhci",
|
||||||
"mediatek,mt8173-xhci";
|
"mediatek,mt8173-xhci";
|
||||||
@ -561,7 +685,8 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
u3phy1: usb-phy@1a1c4000 {
|
u3phy1: usb-phy@1a1c4000 {
|
||||||
compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
|
compatible = "mediatek,mt7623-u3phy",
|
||||||
|
"mediatek,mt2701-u3phy";
|
||||||
reg = <0 0x1a1c4000 0 0x0700>;
|
reg = <0 0x1a1c4000 0 0x0700>;
|
||||||
clocks = <&clk26m>;
|
clocks = <&clk26m>;
|
||||||
clock-names = "u3phya_ref";
|
clock-names = "u3phya_ref";
|
||||||
@ -599,7 +724,8 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
u3phy2: usb-phy@1a244000 {
|
u3phy2: usb-phy@1a244000 {
|
||||||
compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
|
compatible = "mediatek,mt7623-u3phy",
|
||||||
|
"mediatek,mt2701-u3phy";
|
||||||
reg = <0 0x1a244000 0 0x0700>;
|
reg = <0 0x1a244000 0 0x0700>;
|
||||||
clocks = <&clk26m>;
|
clocks = <&clk26m>;
|
||||||
clock-names = "u3phya_ref";
|
clock-names = "u3phya_ref";
|
||||||
@ -621,15 +747,6 @@
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
hifsys: syscon@1a000000 {
|
|
||||||
compatible = "mediatek,mt7623-hifsys",
|
|
||||||
"mediatek,mt2701-hifsys",
|
|
||||||
"syscon";
|
|
||||||
reg = <0 0x1a000000 0 0x1000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
ethsys: syscon@1b000000 {
|
ethsys: syscon@1b000000 {
|
||||||
compatible = "mediatek,mt7623-ethsys",
|
compatible = "mediatek,mt7623-ethsys",
|
||||||
"mediatek,mt2701-ethsys",
|
"mediatek,mt2701-ethsys",
|
||||||
@ -639,7 +756,9 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
eth: ethernet@1b100000 {
|
eth: ethernet@1b100000 {
|
||||||
compatible = "mediatek,mt2701-eth", "syscon";
|
compatible = "mediatek,mt7623-eth",
|
||||||
|
"mediatek,mt2701-eth",
|
||||||
|
"syscon";
|
||||||
reg = <0 0x1b100000 0 0x20000>;
|
reg = <0 0x1b100000 0 0x20000>;
|
||||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
|
||||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
|
||||||
@ -650,6 +769,10 @@
|
|||||||
<ðsys CLK_ETHSYS_GP2>,
|
<ðsys CLK_ETHSYS_GP2>,
|
||||||
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
||||||
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
||||||
|
resets = <ðsys MT2701_ETHSYS_FE_RST>,
|
||||||
|
<ðsys MT2701_ETHSYS_GMAC_RST>,
|
||||||
|
<ðsys MT2701_ETHSYS_PPE_RST>;
|
||||||
|
reset-names = "fe", "gmac", "ppe";
|
||||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||||
mediatek,ethsys = <ðsys>;
|
mediatek,ethsys = <ðsys>;
|
||||||
mediatek,pctl = <&syscfg_pctl_a>;
|
mediatek,pctl = <&syscfg_pctl_a>;
|
||||||
|
|||||||
487
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
Normal file
487
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
Normal file
@ -0,0 +1,487 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2017 Sean Wang <sean.wang@mediatek.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
#include "mt7623.dtsi"
|
||||||
|
#include "mt6323.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Bananapi BPI-R2";
|
||||||
|
compatible = "bananapi,bpi-r2", "mediatek,mt7623";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial2 = &uart2;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
cpu@0 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@1 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@2 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@3 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio_keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&key_pins_a>;
|
||||||
|
|
||||||
|
factory {
|
||||||
|
label = "factory";
|
||||||
|
linux,code = <BTN_0>;
|
||||||
|
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wps {
|
||||||
|
label = "wps";
|
||||||
|
linux,code = <KEY_WPS_BUTTON>;
|
||||||
|
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&led_pins_a>;
|
||||||
|
|
||||||
|
blue {
|
||||||
|
label = "bpi-r2:pio:blue";
|
||||||
|
gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
green {
|
||||||
|
label = "bpi-r2:pio:green";
|
||||||
|
gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
red {
|
||||||
|
label = "bpi-r2:pio:red";
|
||||||
|
gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@80000000 {
|
||||||
|
reg = <0 0x80000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cir {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&cir_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&crypto {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
gmac0: mac@0 {
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <0>;
|
||||||
|
phy-mode = "trgmii";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <1000>;
|
||||||
|
full-duplex;
|
||||||
|
pause;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio: mdio-bus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
switch@0 {
|
||||||
|
compatible = "mediatek,mt7530";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
reset-gpios = <&pio 33 0>;
|
||||||
|
core-supply = <&mt6323_vpa_reg>;
|
||||||
|
io-supply = <&mt6323_vemc3v3_reg>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "wan";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "lan0";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@6 {
|
||||||
|
reg = <6>;
|
||||||
|
label = "cpu";
|
||||||
|
ethernet = <&gmac0>;
|
||||||
|
phy-mode = "trgmii";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <1000>;
|
||||||
|
full-duplex;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c1_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc0 {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_default>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||||
|
status = "okay";
|
||||||
|
bus-width = <8>;
|
||||||
|
max-frequency = <50000000>;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||||
|
vqmmc-supply = <&mt6323_vio18_reg>;
|
||||||
|
non-removable;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc1 {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc1_pins_default>;
|
||||||
|
pinctrl-1 = <&mmc1_pins_uhs>;
|
||||||
|
status = "okay";
|
||||||
|
bus-width = <4>;
|
||||||
|
max-frequency = <50000000>;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
cd-gpios = <&pio 261 0>;
|
||||||
|
vmmc-supply = <&mt6323_vmch_reg>;
|
||||||
|
vqmmc-supply = <&mt6323_vio18_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pio {
|
||||||
|
cir_pins_a:cir@0 {
|
||||||
|
pins_cir {
|
||||||
|
pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c0_pins_a: i2c@0 {
|
||||||
|
pins_i2c0 {
|
||||||
|
pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
|
||||||
|
<MT7623_PIN_76_SCL0_FUNC_SCL0>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1_pins_a: i2c@1 {
|
||||||
|
pin_i2c1 {
|
||||||
|
pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
|
||||||
|
<MT7623_PIN_58_SCL1_FUNC_SCL1>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2s0_pins_a: i2s@0 {
|
||||||
|
pin_i2s0 {
|
||||||
|
pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
|
||||||
|
<MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
|
||||||
|
<MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
|
||||||
|
<MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
|
||||||
|
<MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
|
||||||
|
drive-strength = <MTK_DRIVE_12mA>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2s1_pins_a: i2s@1 {
|
||||||
|
pin_i2s1 {
|
||||||
|
pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
|
||||||
|
<MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
|
||||||
|
<MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
|
||||||
|
<MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
|
||||||
|
<MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
|
||||||
|
drive-strength = <MTK_DRIVE_12mA>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
key_pins_a: keys@0 {
|
||||||
|
pins_keys {
|
||||||
|
pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
|
||||||
|
<MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
|
||||||
|
input-enable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
led_pins_a: leds@0 {
|
||||||
|
pins_leds {
|
||||||
|
pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
|
||||||
|
<MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
|
||||||
|
<MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0_pins_default: mmc0default {
|
||||||
|
pins_cmd_dat {
|
||||||
|
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
|
||||||
|
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
|
||||||
|
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
|
||||||
|
<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
|
||||||
|
<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
|
||||||
|
<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
|
||||||
|
<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
|
||||||
|
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
|
||||||
|
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
|
||||||
|
input-enable;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_clk {
|
||||||
|
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_rst {
|
||||||
|
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0_pins_uhs: mmc0 {
|
||||||
|
pins_cmd_dat {
|
||||||
|
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
|
||||||
|
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
|
||||||
|
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
|
||||||
|
<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
|
||||||
|
<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
|
||||||
|
<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
|
||||||
|
<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
|
||||||
|
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
|
||||||
|
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <MTK_DRIVE_2mA>;
|
||||||
|
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_clk {
|
||||||
|
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
|
||||||
|
drive-strength = <MTK_DRIVE_2mA>;
|
||||||
|
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_rst {
|
||||||
|
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc1_pins_default: mmc1default {
|
||||||
|
pins_cmd_dat {
|
||||||
|
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
|
||||||
|
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
|
||||||
|
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
|
||||||
|
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
|
||||||
|
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <MTK_DRIVE_4mA>;
|
||||||
|
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_clk {
|
||||||
|
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
|
||||||
|
bias-pull-down;
|
||||||
|
drive-strength = <MTK_DRIVE_4mA>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_wp {
|
||||||
|
pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
|
||||||
|
input-enable;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_insert {
|
||||||
|
pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc1_pins_uhs: mmc1 {
|
||||||
|
pins_cmd_dat {
|
||||||
|
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
|
||||||
|
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
|
||||||
|
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
|
||||||
|
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
|
||||||
|
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <MTK_DRIVE_4mA>;
|
||||||
|
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_clk {
|
||||||
|
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
|
||||||
|
drive-strength = <MTK_DRIVE_4mA>;
|
||||||
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pwm_pins_a: pwm@0 {
|
||||||
|
pins_pwm {
|
||||||
|
pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
|
||||||
|
<MT7623_PIN_204_PWM1_FUNC_PWM1>,
|
||||||
|
<MT7623_PIN_205_PWM2_FUNC_PWM2>,
|
||||||
|
<MT7623_PIN_206_PWM3_FUNC_PWM3>,
|
||||||
|
<MT7623_PIN_207_PWM4_FUNC_PWM4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
spi0_pins_a: spi@0 {
|
||||||
|
pins_spi {
|
||||||
|
pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
|
||||||
|
<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
|
||||||
|
<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
|
||||||
|
<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0_pins_a: uart@0 {
|
||||||
|
pins_dat {
|
||||||
|
pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
|
||||||
|
<MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1_pins_a: uart@1 {
|
||||||
|
pins_dat {
|
||||||
|
pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
|
||||||
|
<MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwm {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pwm_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwrap {
|
||||||
|
mt6323 {
|
||||||
|
mt6323led: led {
|
||||||
|
compatible = "mediatek,mt6323-led";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
led@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "bpi-r2:isink:green";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
led@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "bpi-r2:isink:red";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
led@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "bpi-r2:isink:blue";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi0_pins_a>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart0_pins_a>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart1_pins_a>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb1 {
|
||||||
|
vusb33-supply = <&mt6323_vusb_reg>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb2 {
|
||||||
|
vusb33-supply = <&mt6323_vusb_reg>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&u3phy1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&u3phy2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
111
arch/arm/boot/dts/mt7623n-rfb-nand.dts
Normal file
111
arch/arm/boot/dts/mt7623n-rfb-nand.dts
Normal file
@ -0,0 +1,111 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017 MediaTek Inc.
|
||||||
|
* Author: John Crispin <john@phrozen.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7623n-rfb.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "MediaTek MT7623N NAND reference board";
|
||||||
|
compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
|
||||||
|
};
|
||||||
|
|
||||||
|
&bch {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&nandc {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&nand_pins_default>;
|
||||||
|
|
||||||
|
nand@0 {
|
||||||
|
reg = <0>;
|
||||||
|
spare_per_sector = <64>;
|
||||||
|
nand-ecc-mode = "hw";
|
||||||
|
nand-ecc-strength = <12>;
|
||||||
|
nand-ecc-step-size = <1024>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "preloader";
|
||||||
|
reg = <0x0 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@40000 {
|
||||||
|
label = "uboot";
|
||||||
|
reg = <0x40000 0x80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@C0000 {
|
||||||
|
label = "uboot-env";
|
||||||
|
reg = <0xC0000 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@140000 {
|
||||||
|
label = "bootimg";
|
||||||
|
reg = <0x140000 0x2000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@2140000 {
|
||||||
|
label = "recovery";
|
||||||
|
reg = <0x2140000 0x2000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@4140000 {
|
||||||
|
label = "rootfs";
|
||||||
|
reg = <0x4140000 0x1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@5140000 {
|
||||||
|
label = "usrdata";
|
||||||
|
reg = <0x5140000 0x1000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pio {
|
||||||
|
nand_pins_default: nanddefault {
|
||||||
|
pins_ale {
|
||||||
|
pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_dat {
|
||||||
|
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
|
||||||
|
<MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
|
||||||
|
<MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
|
||||||
|
<MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
|
||||||
|
<MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
|
||||||
|
<MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
|
||||||
|
<MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
|
||||||
|
<MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
|
||||||
|
<MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_we {
|
||||||
|
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
92
arch/arm/boot/dts/mt7623n-rfb.dtsi
Normal file
92
arch/arm/boot/dts/mt7623n-rfb.dtsi
Normal file
@ -0,0 +1,92 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017 MediaTek Inc.
|
||||||
|
* Author: John Crispin <john@phrozen.org>
|
||||||
|
* Sean Wang <sean.wang@mediatek.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7623.dtsi"
|
||||||
|
#include "mt6323.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
serial1 = &uart1;
|
||||||
|
serial2 = &uart2;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
cpu0 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu1 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu2 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu3 {
|
||||||
|
proc-supply = <&mt6323_vproc_reg>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@80000000 {
|
||||||
|
reg = <0 0x80000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb_p1_vbus: regulator@0 {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "usb_vbus";
|
||||||
|
regulator-min-microvolt = <5000000>;
|
||||||
|
regulator-max-microvolt = <5000000>;
|
||||||
|
gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
|
||||||
|
enable-active-high;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc0 {
|
||||||
|
vmmc-supply = <&mt6323_vemc3v3_reg>;
|
||||||
|
vqmmc-supply = <&mt6323_vio18_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc1 {
|
||||||
|
vmmc-supply = <&mt6323_vmch_reg>;
|
||||||
|
vqmmc-supply = <&mt6323_vmc_reg>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb1 {
|
||||||
|
vbus-supply = <&usb_p1_vbus>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&u3phy1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue
Block a user