forked from Minki/linux
ARM: shmobile: r8a7778: Common clock framework DT description
Declares all r8a7778 clocks supported by the legacy clock framework, plus tmu2. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> [horms: only included dtsi changes] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ulrich Hecht
Simon Horman
parent
83054671d2
commit
93aa970d2b
@ -16,6 +16,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7778-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -294,4 +295,194 @@
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#size-cells = <0>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External input clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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reg = <0xffc80000 0x80>;
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#clock-cells = <1>;
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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};
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/* Audio clocks; frequencies are set by boards if applicable. */
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "audio_clk_a";
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "audio_clk_b";
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "audio_clk_c";
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};
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/* Fixed ratio clocks */
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g_clk: g_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "g";
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};
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i_clk: i_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "i";
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};
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s3_clk: s3_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "s3";
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};
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s4_clk: s4_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "s4";
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};
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z_clk: z_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "z";
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};
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/* Gate clocks */
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mstp0_clks: mstp0_clks@ffc80030 {
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compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xffc80030 4>;
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clocks = <&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_S>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
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R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
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R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
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R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
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R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
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R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
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R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
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R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
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R8A7778_CLK_SSI3 R8A7778_CLK_SRU
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R8A7778_CLK_HSPI
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>;
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clock-output-names =
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"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
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"scif1", "scif2", "scif3", "scif4", "scif5",
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"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
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"ssi2", "ssi3", "sru", "hspi";
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};
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mstp1_clks: mstp1_clks@ffc80034 {
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compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xffc80034 4>, <0xffc80044 4>;
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clocks = <&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_S>,
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<&cpg_clocks R8A7778_CLK_S>,
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<&cpg_clocks R8A7778_CLK_P>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7778_CLK_ETHER R8A7778_CLK_VIN0
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R8A7778_CLK_VIN1 R8A7778_CLK_USB
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>;
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clock-output-names =
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"ether", "vin0", "vin1", "usb";
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};
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mstp3_clks: mstp3_clks@ffc8003c {
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compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xffc8003c 4>;
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clocks = <&s4_clk>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7778_CLK_MMC R8A7778_CLK_SDHI0
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R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
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R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
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R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
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R8A7778_CLK_SSI8
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>;
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clock-output-names =
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"mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
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"ssi5", "ssi6", "ssi7", "ssi8";
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};
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mstp5_clks: mstp5_clks@ffc80054 {
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compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xffc80054 4>;
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clocks = <&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>,
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<&cpg_clocks R8A7778_CLK_P>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
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R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
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R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
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R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
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R8A7778_CLK_SRU_SRC8
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>;
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clock-output-names =
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"sru-src0", "sru-src1", "sru-src2",
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"sru-src3", "sru-src4", "sru-src5",
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"sru-src6", "sru-src7", "sru-src8";
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};
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};
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};
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