forked from Minki/linux
sky2: Yukon Extreme support
This is basic support for the new Yukon Extreme chip, extracted from the new vendor driver 10.0.4.3. Since this is untested hardware, it has a big fat warning for now. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
62335ab013
commit
9374549428
@ -140,7 +140,7 @@ static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
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static const char *yukon2_name[] = {
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"XL", /* 0xb3 */
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"EC Ultra", /* 0xb4 */
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"UNKNOWN", /* 0xb5 */
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"Extreme", /* 0xb5 */
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"EC", /* 0xb6 */
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"FE", /* 0xb7 */
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};
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@ -211,7 +211,7 @@ static void sky2_power_on(struct sky2_hw *hw)
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else
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sky2_write8(hw, B2_Y2_CLK_GATE, 0);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
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u32 reg1;
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sky2_pci_write32(hw, PCI_DEV_REG3, 0);
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@ -289,8 +289,10 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
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if (sky2->autoneg == AUTONEG_ENABLE &&
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!(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
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if (sky2->autoneg == AUTONEG_ENABLE
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&& !(hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX)) {
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u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
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ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
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@ -317,8 +319,10 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* enable automatic crossover */
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ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
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if (sky2->autoneg == AUTONEG_ENABLE &&
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(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
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if (sky2->autoneg == AUTONEG_ENABLE
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&& (hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX)) {
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ctrl &= ~PHY_M_PC_DSC_MSK;
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ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
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}
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@ -473,7 +477,9 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* restore page register */
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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break;
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case CHIP_ID_YUKON_EC_U:
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case CHIP_ID_YUKON_EX:
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pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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/* select page 3 to access LED control register */
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@ -515,7 +521,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* set page register to 0 */
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gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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} else {
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} else if (hw->chip_id != CHIP_ID_YUKON_EX) {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
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if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
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@ -727,7 +733,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
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sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
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sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
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sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
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if (hw->dev[port]->mtu > ETH_DATA_LEN) {
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@ -1687,7 +1693,9 @@ static void sky2_link_up(struct sky2_port *sky2)
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sky2_write8(hw, SK_REG(port, LNK_LED_REG),
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LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
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if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
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if (hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX) {
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u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
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@ -1780,14 +1788,16 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
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sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
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/* Pause bits are offset (9..8) */
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if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
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if (hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX)
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aux >>= 6;
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sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
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aux & PHY_M_PS_TX_P_EN);
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if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
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&& hw->chip_id != CHIP_ID_YUKON_EC_U)
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&& !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
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sky2->flow_status = FC_NONE;
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if (aux & PHY_M_PS_RX_P_EN)
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@ -2442,6 +2452,7 @@ static inline u32 sky2_mhz(const struct sky2_hw *hw)
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switch (hw->chip_id) {
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case CHIP_ID_YUKON_EC:
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case CHIP_ID_YUKON_EC_U:
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case CHIP_ID_YUKON_EX:
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return 125; /* 125 Mhz */
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case CHIP_ID_YUKON_FE:
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return 100; /* 100 Mhz */
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@ -2474,6 +2485,14 @@ static int __devinit sky2_init(struct sky2_hw *hw)
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return -EOPNOTSUPP;
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}
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if (hw->chip_id == CHIP_ID_YUKON_EX)
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dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
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"Please report success or failure to <netdev@vger.kernel.org>\n");
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/* Make sure and enable all clocks */
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if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
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sky2_pci_write32(hw, PCI_DEV_REG3, 0);
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hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
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/* This rev is really old, and requires untested workarounds */
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@ -2502,6 +2521,12 @@ static void sky2_reset(struct sky2_hw *hw)
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/* disable ASF */
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if (hw->chip_id <= CHIP_ID_YUKON_EC) {
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if (hw->chip_id == CHIP_ID_YUKON_EX) {
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status = sky2_read16(hw, HCU_CCSR);
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status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
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HCU_CCSR_UC_STATE_MSK);
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sky2_write16(hw, HCU_CCSR, status);
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} else
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sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
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sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
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}
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@ -371,12 +371,9 @@ enum {
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/* B2_CHIP_ID 8 bit Chip Identification Number */
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enum {
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CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
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CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
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CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
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CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
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CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
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CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
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CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */
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CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
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CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
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@ -768,6 +765,24 @@ enum {
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POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
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};
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enum {
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SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
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SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
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};
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enum {
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CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
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CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
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CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
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CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
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CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
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CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
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HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
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CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
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HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
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HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
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};
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/* ASF Subsystem Registers (Yukon-2 only) */
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enum {
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B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
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@ -1649,6 +1664,39 @@ enum {
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Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
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Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
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};
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/* HCU_CCSR CPU Control and Status Register */
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enum {
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HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
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HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
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/* Clock Stretching Timeout */
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HCU_CCSR_CS_TO = 1<<25,
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HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
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HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
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HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
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HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
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HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
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HCU_CCSR_SET_SYNC_CPU = 1<<5,
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HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
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HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
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HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
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/* Microcontroller State */
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HCU_CCSR_UC_STATE_MSK = 3,
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HCU_CCSR_UC_STATE_BASE = 1<<0,
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HCU_CCSR_ASF_RESET = 0,
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HCU_CCSR_ASF_HALTED = 1<<1,
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HCU_CCSR_ASF_RUNNING = 1<<0,
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};
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/* HCU_HCSR Host Control and Status Register */
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enum {
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HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
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HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
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HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
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};
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/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
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enum {
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