forked from Minki/linux
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/tg3-2.6
This commit is contained in:
Linus Torvalds
commit
931b11be32
@ -68,8 +68,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.45"
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#define DRV_MODULE_RELDATE "Dec 13, 2005"
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#define DRV_MODULE_VERSION "3.46"
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#define DRV_MODULE_RELDATE "Dec 19, 2005"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -341,6 +341,16 @@ static struct {
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{ "interrupt test (offline)" },
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};
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static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
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{
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writel(val, tp->regs + off);
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}
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static u32 tg3_read32(struct tg3 *tp, u32 off)
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{
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return (readl(tp->regs + off));
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}
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static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
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{
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unsigned long flags;
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@ -411,13 +421,29 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
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return val;
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}
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static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
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/* usec_wait specifies the wait time in usec when writing to certain registers
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* where it is unsafe to read back the register without some delay.
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* GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
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* TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
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*/
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static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
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{
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tp->write32(tp, off, val);
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if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
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!(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
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!(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
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tp->read32(tp, off); /* flush */
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if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
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(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
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/* Non-posted methods */
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tp->write32(tp, off, val);
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else {
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/* Posted method */
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tg3_write32(tp, off, val);
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if (usec_wait)
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udelay(usec_wait);
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tp->read32(tp, off);
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}
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/* Wait again after the read for the posted method to guarantee that
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* the wait time is met.
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*/
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if (usec_wait)
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udelay(usec_wait);
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}
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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@ -438,16 +464,6 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
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readl(mbox);
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}
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static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
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{
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writel(val, tp->regs + off);
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}
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static u32 tg3_read32(struct tg3 *tp, u32 off)
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{
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return (readl(tp->regs + off));
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}
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#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
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#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
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#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
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@ -455,7 +471,8 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
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#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
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#define tw32(reg,val) tp->write32(tp, reg, val)
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#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
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#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
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#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
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#define tr32(reg) tp->read32(tp, reg)
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static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
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@ -595,21 +612,19 @@ static void tg3_switch_clocks(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
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tw32_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl | CLOCK_CTRL_625_CORE);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl | CLOCK_CTRL_625_CORE, 40);
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}
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} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
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tw32_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl |
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(CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
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udelay(40);
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tw32_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl | (CLOCK_CTRL_ALTCLK));
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl |
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(CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
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40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL,
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clock_ctrl | (CLOCK_CTRL_ALTCLK),
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40);
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}
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tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
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}
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#define PHY_BUSY_LOOPS 5000
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@ -1017,12 +1032,15 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
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return;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
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tp_peer = pci_get_drvdata(tp->pdev_peer);
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if (!tp_peer)
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BUG();
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}
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
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struct net_device *dev_peer;
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dev_peer = pci_get_drvdata(tp->pdev_peer);
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if (!dev_peer)
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BUG();
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tp_peer = netdev_priv(dev_peer);
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}
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if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
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(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
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@ -1030,26 +1048,34 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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(tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE0 |
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GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OE2 |
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GRC_LCLCTRL_GPIO_OUTPUT0 |
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GRC_LCLCTRL_GPIO_OUTPUT1));
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE0 |
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GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OE2 |
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GRC_LCLCTRL_GPIO_OUTPUT0 |
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GRC_LCLCTRL_GPIO_OUTPUT1),
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100);
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} else {
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u32 no_gpio2;
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u32 grc_local_ctrl;
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u32 grc_local_ctrl = 0;
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if (tp_peer != tp &&
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(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
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return;
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/* Workaround to prevent overdrawing Amps. */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
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ASIC_REV_5714) {
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grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl, 100);
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}
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/* On 5753 and variants, GPIO2 cannot be used. */
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no_gpio2 = tp->nic_sram_data_cfg &
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NIC_SRAM_DATA_CFG_NO_GPIO2;
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grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
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grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
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GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OE2 |
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GRC_LCLCTRL_GPIO_OUTPUT1 |
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@ -1058,21 +1084,18 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
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GRC_LCLCTRL_GPIO_OUTPUT2);
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}
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl);
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl, 100);
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grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl);
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl, 100);
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if (!no_gpio2) {
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grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl);
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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grc_local_ctrl, 100);
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}
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}
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} else {
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@ -1082,19 +1105,16 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
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return;
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT1));
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT1), 100);
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE1));
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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GRC_LCLCTRL_GPIO_OE1, 100);
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT1));
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udelay(100);
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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(GRC_LCLCTRL_GPIO_OE1 |
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GRC_LCLCTRL_GPIO_OUTPUT1), 100);
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}
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}
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}
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@ -1137,10 +1157,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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udelay(100); /* Delay after power state change */
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/* Switch out of Vaux if it is not a LOM */
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if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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udelay(100);
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}
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if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
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tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
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return 0;
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@ -1239,10 +1257,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
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CLOCK_CTRL_TXCLK_DISABLE);
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tw32_f(TG3PCI_CLOCK_CTRL, base_val |
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CLOCK_CTRL_ALTCLK |
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CLOCK_CTRL_PWRDOWN_PLL133);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
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CLOCK_CTRL_PWRDOWN_PLL133, 40);
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} else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
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/* do nothing */
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} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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@ -1263,11 +1279,11 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
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}
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tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
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40);
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tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
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40);
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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u32 newbits3;
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@ -1281,9 +1297,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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newbits3 = CLOCK_CTRL_44MHZ_CORE;
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}
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tw32_f(TG3PCI_CLOCK_CTRL,
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tp->pci_clock_ctrl | newbits3);
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udelay(40);
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tw32_wait_f(TG3PCI_CLOCK_CTRL,
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tp->pci_clock_ctrl | newbits3, 40);
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}
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}
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@ -1294,7 +1309,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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}
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}
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@ -7959,13 +7975,12 @@ static int tg3_test_memory(struct tg3 *tp)
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u32 offset;
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u32 len;
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} mem_tbl_570x[] = {
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{ 0x00000000, 0x01000},
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{ 0x00000000, 0x00b50},
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{ 0x00002000, 0x1c000},
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{ 0xffffffff, 0x00000}
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}, mem_tbl_5705[] = {
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{ 0x00000100, 0x0000c},
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{ 0x00000200, 0x00008},
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{ 0x00000b50, 0x00400},
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{ 0x00004000, 0x00800},
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{ 0x00006000, 0x01000},
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{ 0x00008000, 0x02000},
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@ -10466,7 +10481,7 @@ static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
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return str;
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}
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static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
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static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
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{
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struct pci_dev *peer;
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unsigned int func, devnr = tp->pdev->devfn & ~7;
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@ -10719,8 +10734,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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tp->rx_pending = 63;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
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tp->pdev_peer = tg3_find_5704_peer(tp);
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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tp->pdev_peer = tg3_find_peer(tp);
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err = tg3_get_device_address(tp);
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if (err) {
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