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ARM: tegra: RAM code access for v4.2-rc1

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The RAM code is used by the memory and external memory controllers to
 determine which set of timings to use for memory frequency scaling.
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Merge tag 'tegra-for-4.2-ramcode' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Merge "ARM: tegra: RAM code access for v4.2-rc1" from Thierry Reding:

The RAM code is used by the memory and external memory controllers to
determine which set of timings to use for memory frequency scaling.

* tag 'tegra-for-4.2-ramcode' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: fuse: Add RAM code reader helper
  of: Document long-ram-code property in nvidia,tegra20-apbmisc
This commit is contained in:
Arnd Bergmann 2015-05-13 17:56:47 +02:00
commit 92d19e26d6
3 changed files with 24 additions and 0 deletions
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2
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
View File

@ -10,3 +10,5 @@ Required properties:
The second entry gives the physical address and length of the The second entry gives the physical address and length of the
registers indicating the strapping options. registers indicating the strapping options.
Optional properties:
- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).

21
drivers/soc/tegra/fuse/tegra-apbmisc.c
View File

@ -28,8 +28,15 @@
#define APBMISC_SIZE 0x64 #define APBMISC_SIZE 0x64
#define FUSE_SKU_INFO 0x10 #define FUSE_SKU_INFO 0x10
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
static void __iomem *apbmisc_base; static void __iomem *apbmisc_base;
static void __iomem *strapping_base; static void __iomem *strapping_base;
static bool long_ram_code;
u32 tegra_read_chipid(void) u32 tegra_read_chipid(void)
{ {
@ -54,6 +61,18 @@ u32 tegra_read_straps(void)
return 0; return 0;
} }
u32 tegra_read_ram_code(void)
{
u32 straps = tegra_read_straps();
if (long_ram_code)
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
else
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
}
static const struct of_device_id apbmisc_match[] __initconst = { static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-apbmisc", }, { .compatible = "nvidia,tegra20-apbmisc", },
{}, {},
@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void)
strapping_base = of_iomap(np, 1); strapping_base = of_iomap(np, 1);
if (!strapping_base) if (!strapping_base)
pr_err("ioremap tegra strapping_base failed\n"); pr_err("ioremap tegra strapping_base failed\n");
long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
} }

1
include/soc/tegra/fuse.h
View File

@ -56,6 +56,7 @@ struct tegra_sku_info {
}; };
u32 tegra_read_straps(void); u32 tegra_read_straps(void);
u32 tegra_read_ram_code(void);
u32 tegra_read_chipid(void); u32 tegra_read_chipid(void);
int tegra_fuse_readl(unsigned long offset, u32 *value); int tegra_fuse_readl(unsigned long offset, u32 *value);