drm/amd/display: change PP_SM defs to 8
DPM level is 8 these were incorrect before. Fix them Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -251,8 +251,8 @@ struct pp_smu_funcs_nv {
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#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
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#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
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#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
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#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
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struct dpm_clock {
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uint32_t Freq; // In MHz
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