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drm/amd/display: Add frame alternate 3D & restrict HW packed on dongles

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[WHY?]
Some projectors support frame alternate 3D modes at 120Hz, but DAL3 does
not create timings. Most active DP to HDMI dongles do not translate
infoframes properly to use HW packing stereo mode.

[HOW?]
Create frame alternate 3D timings for displays that support it. Disable HW
packing 3D mode on DP active dongles.

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2022-02-14 10:47:46 -05:00 committed by Alex Deucher
parent ca6fcfa8d4
commit 91dcfe5fd9
3 changed files with 13 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -2801,6 +2801,17 @@ static bool dp_active_dongle_validate_timing(
return false;
}
/* Check 3D format */
switch (timing->timing_3d_format) {
case TIMING_3D_FORMAT_NONE:
case TIMING_3D_FORMAT_FRAME_ALTERNATE:
/*Only frame alternate 3D is supported on active dongle*/
break;
default:
/*other 3D formats are not supported due to bad infoframe translation */
return false;
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
struct dc_crtc_timing outputTiming = *timing;

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -3093,7 +3093,8 @@ static void dcn10_config_stereo_parameters(
flags->PROGRAM_STEREO = 1;
flags->PROGRAM_POLARITY = 1;
if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
if (timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE ||
timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
enum display_dongle_type dongle = \

11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
View File

@ -707,17 +707,6 @@ bool hubp2_program_surface_flip_and_addr(
REG_UPDATE(VMID_SETTINGS_0,
VMID, address->vmid);
if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
} else {
// turn off stereo if not in stereo
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
}
/* HW automatically latch rest of address register on write to
* DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used