Merge branches 'clk-renesas', 'clk-rockchip', 'clk-const' and 'clk-simplify' into clk-next
* clk-renesas: clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain dt-bindings: clk: emev2: Rename bindings documentation file clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper * clk-rockchip: clk: rockchip: Add clock controller for the rk3308 clk: rockchip: Add dt-binding header for rk3308 dt-bindings: Add bindings for rk3308 clock controller clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver * clk-const: clk: spear: Make structure i2s_sclk_masks constant * clk-simplify: clk/ti: Use kmemdup rather than duplicating its implementation clk: fix devm_platform_ioremap_resource.cocci warnings
This commit is contained in:
Stephen Boyd
commit
91bcbc11d6
Documentation/devicetree/bindings/clock
drivers/clk
bcm
renesas
rockchip
spear
ti
include/dt-bindings/clock
@ -0,0 +1,60 @@
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* Rockchip RK3308 Clock and Reset Unit
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The RK3308 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: CRU should be "rockchip,rk3308-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing, pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
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"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
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"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
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- "mac_clkin" - external MAC clock - optional
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Example: Clock controller node:
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cru: clock-controller@ff500000 {
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compatible = "rockchip,rk3308-cru";
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reg = <0x0 0xff500000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff0a0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0a0000 0x0 0x100>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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@ -146,7 +146,6 @@ static int clk_bcm63xx_probe(struct platform_device *pdev)
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{
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const struct clk_bcm63xx_table_entry *entry, *table;
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struct clk_bcm63xx_hw *hw;
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struct resource *r;
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u8 maxbit = 0;
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int i, ret;
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@ -170,8 +169,7 @@ static int clk_bcm63xx_probe(struct platform_device *pdev)
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for (i = 0; i < maxbit; i++)
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hw->data.hws[i] = ERR_PTR(-ENODEV);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hw->regs = devm_ioremap_resource(&pdev->dev, r);
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hw->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(hw->regs))
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return PTR_ERR(hw->regs);
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@ -334,7 +334,8 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
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return;
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pd->name = np->name;
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pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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pd->attach_dev = cpg_mstp_attach_dev;
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pd->detach_dev = cpg_mstp_detach_dev;
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pm_genpd_init(pd, &pm_domain_always_on_gov, false);
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@ -421,7 +421,8 @@ static int r9a06g032_add_clk_domain(struct device *dev)
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return -ENOMEM;
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pd->name = np->name;
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pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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pd->attach_dev = r9a06g032_attach_dev;
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pd->detach_dev = r9a06g032_detach_dev;
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pm_genpd_init(pd, &pm_domain_always_on_gov, false);
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@ -117,7 +117,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct usb2_clock_sel_priv *priv;
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struct resource *res;
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struct clk *clk;
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struct clk_init_data init;
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@ -125,8 +124,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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@ -551,7 +551,8 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
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genpd = &pd->genpd;
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genpd->name = np->name;
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genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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genpd->attach_dev = cpg_mssr_attach_dev;
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genpd->detach_dev = cpg_mssr_detach_dev;
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pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
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@ -20,6 +20,7 @@ obj-y += clk-rk3128.o
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obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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obj-y += clk-rk3308.o
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obj-y += clk-rk3328.o
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obj-y += clk-rk3368.o
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obj-y += clk-rk3399.o
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955
drivers/clk/rockchip/clk-rk3308.c
Normal file
955
drivers/clk/rockchip/clk-rk3308.c
Normal file
@ -0,0 +1,955 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/rk3308-cru.h>
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#include "clk.h"
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#define RK3308_GRF_SOC_STATUS0 0x380
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enum rk3308_plls {
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apll, dpll, vpll0, vpll1,
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};
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static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
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/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
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RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
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RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
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RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
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RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
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RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
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RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
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RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
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RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
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RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
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RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
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RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
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RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
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RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
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RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
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RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
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RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
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RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
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RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
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RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
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RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
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RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
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RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
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RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
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RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
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RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
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RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
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RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
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RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
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RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
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RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
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RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
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RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
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RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
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RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
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RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
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{ /* sentinel */ },
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};
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#define RK3308_DIV_ACLKM_MASK 0x7
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#define RK3308_DIV_ACLKM_SHIFT 12
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#define RK3308_DIV_PCLK_DBG_MASK 0xf
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#define RK3308_DIV_PCLK_DBG_SHIFT 8
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#define RK3308_CLKSEL0(_aclk_core, _pclk_dbg) \
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{ \
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.reg = RK3308_CLKSEL_CON(0), \
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.val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
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RK3308_DIV_ACLKM_SHIFT) | \
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HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
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RK3308_DIV_PCLK_DBG_SHIFT), \
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}
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#define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3308_CLKSEL0(_aclk_core, _pclk_dbg), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
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RK3308_CPUCLK_RATE(1608000000, 1, 7),
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RK3308_CPUCLK_RATE(1512000000, 1, 7),
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RK3308_CPUCLK_RATE(1488000000, 1, 5),
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RK3308_CPUCLK_RATE(1416000000, 1, 5),
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RK3308_CPUCLK_RATE(1392000000, 1, 5),
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RK3308_CPUCLK_RATE(1296000000, 1, 5),
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RK3308_CPUCLK_RATE(1200000000, 1, 5),
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RK3308_CPUCLK_RATE(1104000000, 1, 5),
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RK3308_CPUCLK_RATE(1008000000, 1, 5),
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RK3308_CPUCLK_RATE(912000000, 1, 5),
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RK3308_CPUCLK_RATE(816000000, 1, 3),
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RK3308_CPUCLK_RATE(696000000, 1, 3),
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RK3308_CPUCLK_RATE(600000000, 1, 3),
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RK3308_CPUCLK_RATE(408000000, 1, 1),
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RK3308_CPUCLK_RATE(312000000, 1, 1),
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RK3308_CPUCLK_RATE(216000000, 1, 1),
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RK3308_CPUCLK_RATE(96000000, 1, 1),
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||||
};
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static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
|
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.core_reg = RK3308_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0xf,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 6,
|
||||
.mux_core_mask = 0x3,
|
||||
};
|
||||
|
||||
PNAME(mux_pll_p) = { "xin24m" };
|
||||
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
|
||||
PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
|
||||
PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
|
||||
PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
|
||||
PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
|
||||
PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
|
||||
PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
|
||||
PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
|
||||
PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
|
||||
PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
|
||||
PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
|
||||
PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
|
||||
PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
|
||||
PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
|
||||
PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
|
||||
PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
|
||||
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
|
||||
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
|
||||
PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
|
||||
PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
|
||||
PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" };
|
||||
PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
|
||||
PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
|
||||
PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
|
||||
PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
|
||||
PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" };
|
||||
PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" };
|
||||
PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
|
||||
PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
|
||||
PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
|
||||
PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" };
|
||||
PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
|
||||
PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
|
||||
PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
|
||||
PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
|
||||
PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" };
|
||||
PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
|
||||
PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
|
||||
PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
|
||||
PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
|
||||
PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" };
|
||||
PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
|
||||
PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
|
||||
PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
|
||||
PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
|
||||
PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" };
|
||||
PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
|
||||
PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
|
||||
PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
|
||||
PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" };
|
||||
PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
|
||||
PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
|
||||
PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
|
||||
PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
|
||||
PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
|
||||
PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
|
||||
|
||||
static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
|
||||
0, RK3308_PLL_CON(0),
|
||||
RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
|
||||
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
|
||||
0, RK3308_PLL_CON(8),
|
||||
RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
|
||||
[vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
|
||||
0, RK3308_PLL_CON(16),
|
||||
RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),
|
||||
[vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
|
||||
0, RK3308_PLL_CON(24),
|
||||
RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
||||
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
|
||||
|
||||
static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata =
|
||||
MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata =
|
||||
MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata =
|
||||
MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata =
|
||||
MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata =
|
||||
MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata =
|
||||
MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata =
|
||||
MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata =
|
||||
MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata =
|
||||
MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(52), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata =
|
||||
MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(54), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata =
|
||||
MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(56), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata =
|
||||
MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(58), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata =
|
||||
MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(60), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata =
|
||||
MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(62), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata =
|
||||
MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(64), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata =
|
||||
MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(66), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata =
|
||||
MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(68), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata =
|
||||
MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(70), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata =
|
||||
MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(48), 14, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata =
|
||||
MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(50), 15, 1, MFLAGS);
|
||||
|
||||
|
||||
static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
|
||||
/*
|
||||
* Clock-Architecture Diagram 1
|
||||
*/
|
||||
|
||||
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_MODE_CON, 8, 2, MFLAGS),
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
||||
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 0, GFLAGS),
|
||||
GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 0, GFLAGS),
|
||||
GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3308_CLKGATE_CON(0), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3308_CLKGATE_CON(0), 1, GFLAGS),
|
||||
|
||||
GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 3, GFLAGS),
|
||||
|
||||
GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(0), 4, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
|
||||
COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 3, GFLAGS),
|
||||
GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 15, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 9, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(12), 0,
|
||||
RK3308_CLKGATE_CON(1), 11, GFLAGS,
|
||||
&rk3308_uart0_fracmux),
|
||||
GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
|
||||
RK3308_CLKGATE_CON(1), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 13, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(15), 0,
|
||||
RK3308_CLKGATE_CON(1), 15, GFLAGS,
|
||||
&rk3308_uart1_fracmux),
|
||||
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
|
||||
RK3308_CLKGATE_CON(2), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 1, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(18), 0,
|
||||
RK3308_CLKGATE_CON(2), 3, GFLAGS,
|
||||
&rk3308_uart2_fracmux),
|
||||
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKGATE_CON(2), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 5, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(21), 0,
|
||||
RK3308_CLKGATE_CON(2), 7, GFLAGS,
|
||||
&rk3308_uart3_fracmux),
|
||||
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
|
||||
RK3308_CLKGATE_CON(2), 8, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 9, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(24), 0,
|
||||
RK3308_CLKGATE_CON(2), 11, GFLAGS,
|
||||
&rk3308_uart4_fracmux),
|
||||
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
|
||||
RK3308_CLKGATE_CON(2), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 13, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 14, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(2), 15, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 1, GFLAGS),
|
||||
COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(15), 0, GFLAGS),
|
||||
COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(15), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 2, GFLAGS),
|
||||
COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 3, GFLAGS),
|
||||
COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 4, GFLAGS),
|
||||
|
||||
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 10, GFLAGS),
|
||||
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 11, GFLAGS),
|
||||
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 12, GFLAGS),
|
||||
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 13, GFLAGS),
|
||||
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 14, GFLAGS),
|
||||
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(3), 15, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
|
||||
RK3308_CLKSEL_CON(33), 0, 11, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 5, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
|
||||
RK3308_CLKSEL_CON(34), 0, 11, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 6, GFLAGS),
|
||||
|
||||
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
|
||||
RK3308_CLKSEL_CON(35), 0, 4, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 7, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
|
||||
RK3308_CLKSEL_CON(35), 4, 2, DFLAGS,
|
||||
RK3308_CLKGATE_CON(3), 8, GFLAGS),
|
||||
|
||||
GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(3), 9, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 4, GFLAGS),
|
||||
COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(1), 6, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(9), 0,
|
||||
RK3308_CLKGATE_CON(1), 7, GFLAGS,
|
||||
&rk3308_dclk_vop_fracmux),
|
||||
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
|
||||
RK3308_CLKGATE_CON(1), 8, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 4
|
||||
*/
|
||||
|
||||
COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 4, GFLAGS),
|
||||
COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 4, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(38), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 6, GFLAGS),
|
||||
COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 6, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(39), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 7, GFLAGS),
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
|
||||
|
||||
COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 8, GFLAGS),
|
||||
COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 8, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(40), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 9, GFLAGS),
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1),
|
||||
|
||||
COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 10, GFLAGS),
|
||||
COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 10, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(41), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 11, GFLAGS),
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1),
|
||||
|
||||
COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0,
|
||||
RK3308_CLKGATE_CON(8), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 14, GFLAGS),
|
||||
MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(43), 14, 1, MFLAGS),
|
||||
GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0,
|
||||
RK3308_CLKGATE_CON(9), 1, GFLAGS),
|
||||
GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0,
|
||||
RK3308_CLKGATE_CON(9), 0, GFLAGS),
|
||||
FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2),
|
||||
FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20),
|
||||
MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
|
||||
RK3308_CLKGATE_CON(8), 15, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 5
|
||||
*/
|
||||
|
||||
GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 12, GFLAGS),
|
||||
|
||||
GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 10, GFLAGS),
|
||||
GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 11, GFLAGS),
|
||||
GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 12, GFLAGS),
|
||||
GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 13, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
|
||||
RK3308_CLKGATE_CON(0), 10, GFLAGS),
|
||||
GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(0), 11, GFLAGS),
|
||||
FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
|
||||
RK3308_CLKGATE_CON(0), 13, GFLAGS),
|
||||
COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(1), 8, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 14, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 6
|
||||
*/
|
||||
|
||||
GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 5, GFLAGS),
|
||||
GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKGATE_CON(4), 6, GFLAGS),
|
||||
|
||||
COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(3), 0,
|
||||
RK3308_CLKGATE_CON(4), 3, GFLAGS,
|
||||
&rk3308_rtc32k_fracmux),
|
||||
MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
|
||||
RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
|
||||
COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(4), 0, 16, DFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 2, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
|
||||
RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 7, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(72), 7, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 8, GFLAGS),
|
||||
|
||||
GATE(0, "clk_wifi_dpll", "dpll", 0,
|
||||
RK3308_CLKGATE_CON(15), 2, GFLAGS),
|
||||
GATE(0, "clk_wifi_vpll0", "vpll0", 0,
|
||||
RK3308_CLKGATE_CON(15), 3, GFLAGS),
|
||||
GATE(0, "clk_wifi_osc", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(15), 4, GFLAGS),
|
||||
COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
|
||||
RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 0, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(44), 7, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(4), 1, GFLAGS),
|
||||
|
||||
GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
|
||||
RK3308_CLKGATE_CON(4), 4, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 7
|
||||
*/
|
||||
|
||||
COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
|
||||
RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
|
||||
RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 2, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 3, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(47), 0,
|
||||
RK3308_CLKGATE_CON(10), 4, GFLAGS,
|
||||
&rk3308_pdm_fracmux),
|
||||
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
|
||||
RK3308_CLKGATE_CON(10), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 12, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(53), 0,
|
||||
RK3308_CLKGATE_CON(10), 13, GFLAGS,
|
||||
&rk3308_i2s0_8ch_tx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(52), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 0, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(55), 0,
|
||||
RK3308_CLKGATE_CON(11), 1, GFLAGS,
|
||||
&rk3308_i2s0_8ch_rx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 2, GFLAGS),
|
||||
GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0,
|
||||
RK3308_CLKGATE_CON(11), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 4, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(57), 0,
|
||||
RK3308_CLKGATE_CON(11), 5, GFLAGS,
|
||||
&rk3308_i2s1_8ch_tx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 6, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(56), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 8, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(59), 0,
|
||||
RK3308_CLKGATE_CON(11), 9, GFLAGS,
|
||||
&rk3308_i2s1_8ch_rx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 10, GFLAGS),
|
||||
GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0,
|
||||
RK3308_CLKGATE_CON(11), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 12, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(61), 0,
|
||||
RK3308_CLKGATE_CON(11), 13, GFLAGS,
|
||||
&rk3308_i2s2_8ch_tx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(60), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(11), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 0, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(63), 0,
|
||||
RK3308_CLKGATE_CON(12), 1, GFLAGS,
|
||||
&rk3308_i2s2_8ch_rx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 2, GFLAGS),
|
||||
GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0,
|
||||
RK3308_CLKGATE_CON(12), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 4, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(65), 0,
|
||||
RK3308_CLKGATE_CON(12), 5, GFLAGS,
|
||||
&rk3308_i2s3_8ch_tx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 6, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(64), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 8, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(67), 0,
|
||||
RK3308_CLKGATE_CON(12), 9, GFLAGS,
|
||||
&rk3308_i2s3_8ch_rx_fracmux),
|
||||
COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 10, GFLAGS),
|
||||
GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0,
|
||||
RK3308_CLKGATE_CON(12), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 12, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(69), 0,
|
||||
RK3308_CLKGATE_CON(12), 13, GFLAGS,
|
||||
&rk3308_i2s0_2ch_fracmux),
|
||||
GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
|
||||
RK3308_CLKGATE_CON(12), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(68), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(12), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
|
||||
RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(13), 0, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(71), 0,
|
||||
RK3308_CLKGATE_CON(13), 1, GFLAGS,
|
||||
&rk3308_i2s1_2ch_fracmux),
|
||||
GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
|
||||
RK3308_CLKGATE_CON(13), 2, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(70), 15, 1, MFLAGS,
|
||||
RK3308_CLKGATE_CON(13), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 6, GFLAGS),
|
||||
COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 6, GFLAGS),
|
||||
MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(48), 12, 1, MFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(49), 0,
|
||||
RK3308_CLKGATE_CON(10), 7, GFLAGS,
|
||||
&rk3308_spdif_tx_fracmux),
|
||||
GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
|
||||
RK3308_CLKGATE_CON(10), 8, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 9, GFLAGS),
|
||||
COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
|
||||
RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3308_CLKGATE_CON(10), 9, GFLAGS),
|
||||
MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
RK3308_CLKSEL_CON(50), 14, 1, MFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
|
||||
RK3308_CLKSEL_CON(51), 0,
|
||||
RK3308_CLKGATE_CON(10), 10, GFLAGS,
|
||||
&rk3308_spdif_rx_fracmux),
|
||||
GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
|
||||
RK3308_CLKGATE_CON(10), 11, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 8
|
||||
*/
|
||||
|
||||
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS),
|
||||
GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS),
|
||||
GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS),
|
||||
GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS),
|
||||
GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS),
|
||||
GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS),
|
||||
GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS),
|
||||
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS),
|
||||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS),
|
||||
GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS),
|
||||
GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS),
|
||||
GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS),
|
||||
GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS),
|
||||
GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS),
|
||||
GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS),
|
||||
GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS),
|
||||
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
|
||||
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS),
|
||||
GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS),
|
||||
GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS),
|
||||
GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS),
|
||||
GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS),
|
||||
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS),
|
||||
|
||||
GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS),
|
||||
GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS),
|
||||
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
|
||||
GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
|
||||
/* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
|
||||
SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
|
||||
/* aclk_dmac1 is controlled by sgrf_clkgat_con. */
|
||||
SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
|
||||
/* watchdog pclk is controlled by sgrf_clkgat_con. */
|
||||
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
|
||||
|
||||
GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
|
||||
GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
|
||||
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS),
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
|
||||
GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
|
||||
GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
|
||||
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
|
||||
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
|
||||
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
|
||||
GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
|
||||
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS),
|
||||
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS),
|
||||
GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS),
|
||||
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS),
|
||||
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS),
|
||||
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS),
|
||||
GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS),
|
||||
GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS),
|
||||
GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS),
|
||||
GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS),
|
||||
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS),
|
||||
GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS),
|
||||
GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS),
|
||||
GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
|
||||
GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
|
||||
GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
|
||||
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
|
||||
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
|
||||
GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
|
||||
GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
|
||||
};
|
||||
|
||||
static const char *const rk3308_critical_clocks[] __initconst = {
|
||||
"aclk_bus",
|
||||
"hclk_bus",
|
||||
"pclk_bus",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
"hclk_audio",
|
||||
"pclk_audio",
|
||||
"sclk_ddrc",
|
||||
};
|
||||
|
||||
static void __init rk3308_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_register_plls(ctx, rk3308_pll_clks,
|
||||
ARRAY_SIZE(rk3308_pll_clks),
|
||||
RK3308_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(ctx, rk3308_clk_branches,
|
||||
ARRAY_SIZE(rk3308_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3308_critical_clocks,
|
||||
ARRAY_SIZE(rk3308_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
|
||||
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
|
||||
&rk3308_cpuclk_data, rk3308_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3308_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL);
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
|
||||
@ -122,7 +122,6 @@ PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
|
||||
PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
|
||||
PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
|
||||
PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
|
||||
PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
|
||||
PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
|
||||
PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
|
||||
PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
|
||||
|
||||
@ -121,6 +121,19 @@ struct clk;
|
||||
#define RK3288_EMMC_CON0 0x218
|
||||
#define RK3288_EMMC_CON1 0x21c
|
||||
|
||||
#define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3308_GLB_SRST_FST 0xb8
|
||||
#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
|
||||
#define RK3308_MODE_CON 0xa0
|
||||
#define RK3308_SDMMC_CON0 0x480
|
||||
#define RK3308_SDMMC_CON1 0x484
|
||||
#define RK3308_SDIO_CON0 0x488
|
||||
#define RK3308_SDIO_CON1 0x48c
|
||||
#define RK3308_EMMC_CON0 0x490
|
||||
#define RK3308_EMMC_CON1 0x494
|
||||
|
||||
#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
||||
|
||||
@ -335,7 +335,7 @@ static const struct aux_clk_masks i2s_prs1_masks = {
|
||||
};
|
||||
|
||||
/* i2s sclk (bit clock) syynthesizers masks */
|
||||
static struct aux_clk_masks i2s_sclk_masks = {
|
||||
static const struct aux_clk_masks i2s_sclk_masks = {
|
||||
.eq_sel_mask = AUX_EQ_SEL_MASK,
|
||||
.eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
|
||||
.eq1_mask = AUX_EQ1_SEL,
|
||||
|
||||
@ -292,14 +292,12 @@ static void __init of_ti_dpll_setup(struct device_node *node,
|
||||
struct dpll_data *dd = NULL;
|
||||
u8 dpll_mode = 0;
|
||||
|
||||
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
|
||||
dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
init = kzalloc(sizeof(*init), GFP_KERNEL);
|
||||
if (!dd || !clk_hw || !init)
|
||||
goto cleanup;
|
||||
|
||||
memcpy(dd, ddt, sizeof(*dd));
|
||||
|
||||
clk_hw->dpll_data = dd;
|
||||
clk_hw->ops = &clkhwops_omap3_dpll;
|
||||
clk_hw->hw.init = init;
|
||||
|
||||
387
include/dt-bindings/clock/rk3308-cru.h
Normal file
387
include/dt-bindings/clock/rk3308-cru.h
Normal file
@ -0,0 +1,387 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
|
||||
* Author: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_VPLL0 3
|
||||
#define PLL_VPLL1 4
|
||||
#define ARMCLK 5
|
||||
|
||||
/* sclk (special clocks) */
|
||||
#define USB480M 14
|
||||
#define SCLK_RTC32K 15
|
||||
#define SCLK_PVTM_CORE 16
|
||||
#define SCLK_UART0 17
|
||||
#define SCLK_UART1 18
|
||||
#define SCLK_UART2 19
|
||||
#define SCLK_UART3 20
|
||||
#define SCLK_UART4 21
|
||||
#define SCLK_I2C0 22
|
||||
#define SCLK_I2C1 23
|
||||
#define SCLK_I2C2 24
|
||||
#define SCLK_I2C3 25
|
||||
#define SCLK_PWM0 26
|
||||
#define SCLK_SPI0 27
|
||||
#define SCLK_SPI1 28
|
||||
#define SCLK_SPI2 29
|
||||
#define SCLK_TIMER0 30
|
||||
#define SCLK_TIMER1 31
|
||||
#define SCLK_TIMER2 32
|
||||
#define SCLK_TIMER3 33
|
||||
#define SCLK_TIMER4 34
|
||||
#define SCLK_TIMER5 35
|
||||
#define SCLK_TSADC 36
|
||||
#define SCLK_SARADC 37
|
||||
#define SCLK_OTP 38
|
||||
#define SCLK_OTP_USR 39
|
||||
#define SCLK_CPU_BOOST 40
|
||||
#define SCLK_CRYPTO 41
|
||||
#define SCLK_CRYPTO_APK 42
|
||||
#define SCLK_NANDC_DIV 43
|
||||
#define SCLK_NANDC_DIV50 44
|
||||
#define SCLK_NANDC 45
|
||||
#define SCLK_SDMMC_DIV 46
|
||||
#define SCLK_SDMMC_DIV50 47
|
||||
#define SCLK_SDMMC 48
|
||||
#define SCLK_SDMMC_DRV 49
|
||||
#define SCLK_SDMMC_SAMPLE 50
|
||||
#define SCLK_SDIO_DIV 51
|
||||
#define SCLK_SDIO_DIV50 52
|
||||
#define SCLK_SDIO 53
|
||||
#define SCLK_SDIO_DRV 54
|
||||
#define SCLK_SDIO_SAMPLE 55
|
||||
#define SCLK_EMMC_DIV 56
|
||||
#define SCLK_EMMC_DIV50 57
|
||||
#define SCLK_EMMC 58
|
||||
#define SCLK_EMMC_DRV 59
|
||||
#define SCLK_EMMC_SAMPLE 60
|
||||
#define SCLK_SFC 61
|
||||
#define SCLK_OTG_ADP 62
|
||||
#define SCLK_MAC_SRC 63
|
||||
#define SCLK_MAC 64
|
||||
#define SCLK_MAC_REF 65
|
||||
#define SCLK_MAC_RX_TX 66
|
||||
#define SCLK_MAC_RMII 67
|
||||
#define SCLK_DDR_MON_TIMER 68
|
||||
#define SCLK_DDR_MON 69
|
||||
#define SCLK_DDRCLK 70
|
||||
#define SCLK_PMU 71
|
||||
#define SCLK_USBPHY_REF 72
|
||||
#define SCLK_WIFI 73
|
||||
#define SCLK_PVTM_PMU 74
|
||||
#define SCLK_PDM 75
|
||||
#define SCLK_I2S0_8CH_TX 76
|
||||
#define SCLK_I2S0_8CH_TX_OUT 77
|
||||
#define SCLK_I2S0_8CH_RX 78
|
||||
#define SCLK_I2S0_8CH_RX_OUT 79
|
||||
#define SCLK_I2S1_8CH_TX 80
|
||||
#define SCLK_I2S1_8CH_TX_OUT 81
|
||||
#define SCLK_I2S1_8CH_RX 82
|
||||
#define SCLK_I2S1_8CH_RX_OUT 83
|
||||
#define SCLK_I2S2_8CH_TX 84
|
||||
#define SCLK_I2S2_8CH_TX_OUT 85
|
||||
#define SCLK_I2S2_8CH_RX 86
|
||||
#define SCLK_I2S2_8CH_RX_OUT 87
|
||||
#define SCLK_I2S3_8CH_TX 88
|
||||
#define SCLK_I2S3_8CH_TX_OUT 89
|
||||
#define SCLK_I2S3_8CH_RX 90
|
||||
#define SCLK_I2S3_8CH_RX_OUT 91
|
||||
#define SCLK_I2S0_2CH 92
|
||||
#define SCLK_I2S0_2CH_OUT 93
|
||||
#define SCLK_I2S1_2CH 94
|
||||
#define SCLK_I2S1_2CH_OUT 95
|
||||
#define SCLK_SPDIF_TX_DIV 96
|
||||
#define SCLK_SPDIF_TX_DIV50 97
|
||||
#define SCLK_SPDIF_TX 98
|
||||
#define SCLK_SPDIF_RX_DIV 99
|
||||
#define SCLK_SPDIF_RX_DIV50 100
|
||||
#define SCLK_SPDIF_RX 101
|
||||
#define SCLK_I2S0_8CH_TX_MUX 102
|
||||
#define SCLK_I2S0_8CH_RX_MUX 103
|
||||
#define SCLK_I2S1_8CH_TX_MUX 104
|
||||
#define SCLK_I2S1_8CH_RX_MUX 105
|
||||
#define SCLK_I2S2_8CH_TX_MUX 106
|
||||
#define SCLK_I2S2_8CH_RX_MUX 107
|
||||
#define SCLK_I2S3_8CH_TX_MUX 108
|
||||
#define SCLK_I2S3_8CH_RX_MUX 109
|
||||
#define SCLK_I2S0_8CH_TX_SRC 110
|
||||
#define SCLK_I2S0_8CH_RX_SRC 111
|
||||
#define SCLK_I2S1_8CH_TX_SRC 112
|
||||
#define SCLK_I2S1_8CH_RX_SRC 113
|
||||
#define SCLK_I2S2_8CH_TX_SRC 114
|
||||
#define SCLK_I2S2_8CH_RX_SRC 115
|
||||
#define SCLK_I2S3_8CH_TX_SRC 116
|
||||
#define SCLK_I2S3_8CH_RX_SRC 117
|
||||
#define SCLK_I2S0_2CH_SRC 118
|
||||
#define SCLK_I2S1_2CH_SRC 119
|
||||
#define SCLK_PWM1 120
|
||||
#define SCLK_PWM2 121
|
||||
#define SCLK_OWIRE 122
|
||||
|
||||
/* dclk */
|
||||
#define DCLK_VOP 125
|
||||
|
||||
/* aclk */
|
||||
#define ACLK_BUS_SRC 130
|
||||
#define ACLK_BUS 131
|
||||
#define ACLK_PERI_SRC 132
|
||||
#define ACLK_PERI 133
|
||||
#define ACLK_MAC 134
|
||||
#define ACLK_CRYPTO 135
|
||||
#define ACLK_VOP 136
|
||||
#define ACLK_GIC 137
|
||||
#define ACLK_DMAC0 138
|
||||
#define ACLK_DMAC1 139
|
||||
|
||||
/* hclk */
|
||||
#define HCLK_BUS 150
|
||||
#define HCLK_PERI 151
|
||||
#define HCLK_AUDIO 152
|
||||
#define HCLK_NANDC 153
|
||||
#define HCLK_SDMMC 154
|
||||
#define HCLK_SDIO 155
|
||||
#define HCLK_EMMC 156
|
||||
#define HCLK_SFC 157
|
||||
#define HCLK_OTG 158
|
||||
#define HCLK_HOST 159
|
||||
#define HCLK_HOST_ARB 160
|
||||
#define HCLK_PDM 161
|
||||
#define HCLK_SPDIFTX 162
|
||||
#define HCLK_SPDIFRX 163
|
||||
#define HCLK_I2S0_8CH 164
|
||||
#define HCLK_I2S1_8CH 165
|
||||
#define HCLK_I2S2_8CH 166
|
||||
#define HCLK_I2S3_8CH 167
|
||||
#define HCLK_I2S0_2CH 168
|
||||
#define HCLK_I2S1_2CH 169
|
||||
#define HCLK_VAD 170
|
||||
#define HCLK_CRYPTO 171
|
||||
#define HCLK_VOP 172
|
||||
|
||||
/* pclk */
|
||||
#define PCLK_BUS 190
|
||||
#define PCLK_DDR 191
|
||||
#define PCLK_PERI 192
|
||||
#define PCLK_PMU 193
|
||||
#define PCLK_AUDIO 194
|
||||
#define PCLK_MAC 195
|
||||
#define PCLK_ACODEC 196
|
||||
#define PCLK_UART0 197
|
||||
#define PCLK_UART1 198
|
||||
#define PCLK_UART2 199
|
||||
#define PCLK_UART3 200
|
||||
#define PCLK_UART4 201
|
||||
#define PCLK_I2C0 202
|
||||
#define PCLK_I2C1 203
|
||||
#define PCLK_I2C2 204
|
||||
#define PCLK_I2C3 205
|
||||
#define PCLK_PWM0 206
|
||||
#define PCLK_SPI0 207
|
||||
#define PCLK_SPI1 208
|
||||
#define PCLK_SPI2 209
|
||||
#define PCLK_SARADC 210
|
||||
#define PCLK_TSADC 211
|
||||
#define PCLK_TIMER 212
|
||||
#define PCLK_OTP_NS 213
|
||||
#define PCLK_WDT 214
|
||||
#define PCLK_GPIO0 215
|
||||
#define PCLK_GPIO1 216
|
||||
#define PCLK_GPIO2 217
|
||||
#define PCLK_GPIO3 218
|
||||
#define PCLK_GPIO4 219
|
||||
#define PCLK_SGRF 220
|
||||
#define PCLK_GRF 221
|
||||
#define PCLK_USBSD_DET 222
|
||||
#define PCLK_DDR_UPCTL 223
|
||||
#define PCLK_DDR_MON 224
|
||||
#define PCLK_DDRPHY 225
|
||||
#define PCLK_DDR_STDBY 226
|
||||
#define PCLK_USB_GRF 227
|
||||
#define PCLK_CRU 228
|
||||
#define PCLK_OTP_PHY 229
|
||||
#define PCLK_CPU_BOOST 230
|
||||
#define PCLK_PWM1 231
|
||||
#define PCLK_PWM2 232
|
||||
#define PCLK_CAN 233
|
||||
#define PCLK_OWIRE 234
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_OWIRE + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_CORE_NOC 13
|
||||
#define SRST_STRC_A 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
/* cru_softrst_con1 */
|
||||
#define SRST_DAP 16
|
||||
#define SRST_CORE_PVTM 17
|
||||
#define SRST_CORE_PRF 18
|
||||
#define SRST_CORE_GRF 19
|
||||
#define SRST_DDRUPCTL 20
|
||||
#define SRST_DDRUPCTL_P 22
|
||||
#define SRST_MSCH 23
|
||||
#define SRST_DDRMON_P 25
|
||||
#define SRST_DDRSTDBY_P 26
|
||||
#define SRST_DDRSTDBY 27
|
||||
#define SRST_DDRPHY 28
|
||||
#define SRST_DDRPHY_DIV 29
|
||||
#define SRST_DDRPHY_P 30
|
||||
|
||||
/* cru_softrst_con2 */
|
||||
#define SRST_BUS_NIU_H 32
|
||||
#define SRST_USB_NIU_P 33
|
||||
#define SRST_CRYPTO_A 34
|
||||
#define SRST_CRYPTO_H 35
|
||||
#define SRST_CRYPTO 36
|
||||
#define SRST_CRYPTO_APK 37
|
||||
#define SRST_VOP_A 38
|
||||
#define SRST_VOP_H 39
|
||||
#define SRST_VOP_D 40
|
||||
#define SRST_INTMEM_A 41
|
||||
#define SRST_ROM_H 42
|
||||
#define SRST_GIC_A 43
|
||||
#define SRST_UART0_P 44
|
||||
#define SRST_UART0 45
|
||||
#define SRST_UART1_P 46
|
||||
#define SRST_UART1 47
|
||||
|
||||
/* cru_softrst_con3 */
|
||||
#define SRST_UART2_P 48
|
||||
#define SRST_UART2 49
|
||||
#define SRST_UART3_P 50
|
||||
#define SRST_UART3 51
|
||||
#define SRST_UART4_P 52
|
||||
#define SRST_UART4 53
|
||||
#define SRST_I2C0_P 54
|
||||
#define SRST_I2C0 55
|
||||
#define SRST_I2C1_P 56
|
||||
#define SRST_I2C1 57
|
||||
#define SRST_I2C2_P 58
|
||||
#define SRST_I2C2 59
|
||||
#define SRST_I2C3_P 60
|
||||
#define SRST_I2C3 61
|
||||
#define SRST_PWM0_P 62
|
||||
#define SRST_PWM0 63
|
||||
|
||||
/* cru_softrst_con4 */
|
||||
#define SRST_SPI0_P 64
|
||||
#define SRST_SPI0 65
|
||||
#define SRST_SPI1_P 66
|
||||
#define SRST_SPI1 67
|
||||
#define SRST_SPI2_P 68
|
||||
#define SRST_SPI2 69
|
||||
#define SRST_SARADC_P 70
|
||||
#define SRST_TSADC_P 71
|
||||
#define SRST_TSADC 72
|
||||
#define SRST_TIMER0_P 73
|
||||
#define SRST_TIMER0 74
|
||||
#define SRST_TIMER1 75
|
||||
#define SRST_TIMER2 76
|
||||
#define SRST_TIMER3 77
|
||||
#define SRST_TIMER4 78
|
||||
#define SRST_TIMER5 79
|
||||
|
||||
/* cru_softrst_con5 */
|
||||
#define SRST_OTP_NS_P 80
|
||||
#define SRST_OTP_NS_SBPI 81
|
||||
#define SRST_OTP_NS_USR 82
|
||||
#define SRST_OTP_PHY_P 83
|
||||
#define SRST_OTP_PHY 84
|
||||
#define SRST_GPIO0_P 86
|
||||
#define SRST_GPIO1_P 87
|
||||
#define SRST_GPIO2_P 88
|
||||
#define SRST_GPIO3_P 89
|
||||
#define SRST_GPIO4_P 90
|
||||
#define SRST_GRF_P 91
|
||||
#define SRST_USBSD_DET_P 92
|
||||
#define SRST_PMU 93
|
||||
#define SRST_PMU_PVTM 94
|
||||
#define SRST_USB_GRF_P 95
|
||||
|
||||
/* cru_softrst_con6 */
|
||||
#define SRST_CPU_BOOST 96
|
||||
#define SRST_CPU_BOOST_P 97
|
||||
#define SRST_PWM1_P 98
|
||||
#define SRST_PWM1 99
|
||||
#define SRST_PWM2_P 100
|
||||
#define SRST_PWM2 101
|
||||
#define SRST_PERI_NIU_A 104
|
||||
#define SRST_PERI_NIU_H 105
|
||||
#define SRST_PERI_NIU_p 106
|
||||
#define SRST_USB2OTG_H 107
|
||||
#define SRST_USB2OTG 108
|
||||
#define SRST_USB2OTG_ADP 109
|
||||
#define SRST_USB2HOST_H 110
|
||||
#define SRST_USB2HOST_ARB_H 111
|
||||
|
||||
/* cru_softrst_con7 */
|
||||
#define SRST_USB2HOST_AUX_H 112
|
||||
#define SRST_USB2HOST_EHCI 113
|
||||
#define SRST_USB2HOST 114
|
||||
#define SRST_USBPHYPOR 115
|
||||
#define SRST_UTMI0 116
|
||||
#define SRST_UTMI1 117
|
||||
#define SRST_SDIO_H 118
|
||||
#define SRST_EMMC_H 119
|
||||
#define SRST_SFC_H 120
|
||||
#define SRST_SFC 121
|
||||
#define SRST_SD_H 122
|
||||
#define SRST_NANDC_H 123
|
||||
#define SRST_NANDC_N 124
|
||||
#define SRST_MAC_A 125
|
||||
#define SRST_CAN_P 126
|
||||
#define SRST_OWIRE_P 127
|
||||
|
||||
/* cru_softrst_con8 */
|
||||
#define SRST_AUDIO_NIU_H 128
|
||||
#define SRST_AUDIO_NIU_P 129
|
||||
#define SRST_PDM_H 130
|
||||
#define SRST_PDM_M 131
|
||||
#define SRST_SPDIFTX_H 132
|
||||
#define SRST_SPDIFTX_M 133
|
||||
#define SRST_SPDIFRX_H 134
|
||||
#define SRST_SPDIFRX_M 135
|
||||
#define SRST_I2S0_8CH_H 136
|
||||
#define SRST_I2S0_8CH_TX_M 137
|
||||
#define SRST_I2S0_8CH_RX_M 138
|
||||
#define SRST_I2S1_8CH_H 139
|
||||
#define SRST_I2S1_8CH_TX_M 140
|
||||
#define SRST_I2S1_8CH_RX_M 141
|
||||
#define SRST_I2S2_8CH_H 142
|
||||
#define SRST_I2S2_8CH_TX_M 143
|
||||
|
||||
/* cru_softrst_con9 */
|
||||
#define SRST_I2S2_8CH_RX_M 144
|
||||
#define SRST_I2S3_8CH_H 145
|
||||
#define SRST_I2S3_8CH_TX_M 146
|
||||
#define SRST_I2S3_8CH_RX_M 147
|
||||
#define SRST_I2S0_2CH_H 148
|
||||
#define SRST_I2S0_2CH_M 149
|
||||
#define SRST_I2S1_2CH_H 150
|
||||
#define SRST_I2S1_2CH_M 151
|
||||
#define SRST_VAD_H 152
|
||||
#define SRST_ACODEC_P 153
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user