forked from Minki/linux
openrisc: use shadow registers to save regs on exception
Previously, the area between 0x0-0x100 have been used as a "scratch" memory area to temporarily store regs during exception entry. In a multi-core environment, this will not work. This change is to use shadow registers for nested context. Currently only the "critical" temp load/stores are covered, the EMERGENCY_PRINT ones are left as is (when they are used, it's game over anyway), they need to be handled as well in the future. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stefan Kristiansson
Stafford Horne
parent
ddc92bec6d
commit
91993c8c2e
@ -124,6 +124,17 @@ config OPENRISC_NO_SPR_SR_DSX
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Say N here if you know that your OpenRISC processor has
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SPR_SR_DSX bit implemented. Say Y if you are unsure.
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config OPENRISC_HAVE_SHADOW_GPRS
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bool "Support for shadow gpr files" if !SMP
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default y if SMP
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help
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Say Y here if your OpenRISC processor features shadowed
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register files. They will in such case be used as a
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scratch reg storage on exception entry.
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On SMP systems, this feature is mandatory.
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On a unicore system it's safe to say N here if you are unsure.
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config CMDLINE
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string "Default kernel command string"
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default ""
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@ -49,9 +49,31 @@
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/* ============================================[ tmp store locations ]=== */
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#define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
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/*
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* emergency_print temporary stores
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*/
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#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
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#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
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#define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
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#define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
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#define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
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#define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
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#define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
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#define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
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#define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
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#define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
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#define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
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#define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
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#define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
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#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
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#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
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#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
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@ -70,13 +92,28 @@
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#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
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#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
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#endif
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/*
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* TLB miss handlers temorary stores
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*/
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#define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
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#define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
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#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
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#define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
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#define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
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#define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
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#define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
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#define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
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#define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
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#define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
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#define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
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#define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
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#define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
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#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
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#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
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#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
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@ -92,26 +129,32 @@
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#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
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#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
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#endif
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/*
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* EXCEPTION_HANDLE temporary stores
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*/
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#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
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#define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
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#define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
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#define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
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#define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
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#define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
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#define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
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#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
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#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
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#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
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#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
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#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
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#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
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#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
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#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
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/*
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* For UNHANLDED_EXCEPTION
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*/
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#define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
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#define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
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#endif
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/* =========================================================[ macros ]=== */
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@ -226,7 +269,7 @@
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*
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*/
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#define UNHANDLED_EXCEPTION(handler) \
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EXCEPTION_T_STORE_GPR31 ;\
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EXCEPTION_T_STORE_GPR30 ;\
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EXCEPTION_T_STORE_GPR10 ;\
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EXCEPTION_T_STORE_SP ;\
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/* temporary store r3, r9 into r1, r10 */ ;\
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@ -255,35 +298,35 @@
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/* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
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/* r12: temp, syscall indicator, r13 temp */ ;\
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l.addi r1,r1,-(INT_FRAME_SIZE) ;\
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/* r1 is KSP, r31 is __pa(KSP) */ ;\
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tophys (r31,r1) ;\
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l.sw PT_GPR12(r31),r12 ;\
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/* r1 is KSP, r30 is __pa(KSP) */ ;\
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tophys (r30,r1) ;\
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l.sw PT_GPR12(r30),r12 ;\
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l.mfspr r12,r0,SPR_EPCR_BASE ;\
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l.sw PT_PC(r31),r12 ;\
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l.sw PT_PC(r30),r12 ;\
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l.mfspr r12,r0,SPR_ESR_BASE ;\
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l.sw PT_SR(r31),r12 ;\
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l.sw PT_SR(r30),r12 ;\
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/* save r31 */ ;\
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EXCEPTION_T_LOAD_GPR31(r12) ;\
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l.sw PT_GPR31(r31),r12 ;\
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EXCEPTION_T_LOAD_GPR30(r12) ;\
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l.sw PT_GPR30(r30),r12 ;\
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/* save r10 as was prior to exception */ ;\
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EXCEPTION_T_LOAD_GPR10(r12) ;\
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l.sw PT_GPR10(r31),r12 ;\
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l.sw PT_GPR10(r30),r12 ;\
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/* save PT_SP as was prior to exception */ ;\
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EXCEPTION_T_LOAD_SP(r12) ;\
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l.sw PT_SP(r31),r12 ;\
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l.sw PT_GPR13(r31),r13 ;\
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l.sw PT_SP(r30),r12 ;\
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l.sw PT_GPR13(r30),r13 ;\
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/* --> */ ;\
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/* save exception r4, set r4 = EA */ ;\
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l.sw PT_GPR4(r31),r4 ;\
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l.sw PT_GPR4(r30),r4 ;\
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l.mfspr r4,r0,SPR_EEAR_BASE ;\
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/* r12 == 1 if we come from syscall */ ;\
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CLEAR_GPR(r12) ;\
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/* ----- play a MMU trick ----- */ ;\
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l.ori r31,r0,(EXCEPTION_SR) ;\
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l.mtspr r0,r31,SPR_ESR_BASE ;\
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l.ori r30,r0,(EXCEPTION_SR) ;\
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l.mtspr r0,r30,SPR_ESR_BASE ;\
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/* r31: EA address of handler */ ;\
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LOAD_SYMBOL_2_GPR(r31,handler) ;\
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l.mtspr r0,r31,SPR_EPCR_BASE ;\
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LOAD_SYMBOL_2_GPR(r30,handler) ;\
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l.mtspr r0,r30,SPR_EPCR_BASE ;\
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l.rfe
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/* =====================================================[ exceptions] === */
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