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drm/amdgpu/powerplay: split out common smu7 BACO code

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Several of the BACO functions are common across smu7-based
asics.  Split the common code out.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2019-02-15 17:39:33 -05:00
parent 56f68f18e0
commit 912a0bf574
11 changed files with 132 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
View File

@ -37,7 +37,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
ci_baco.o
ci_baco.o smu7_baco.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

34
drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
View File

@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
};
int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
*cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
return 0;
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
*cap = true;
return 0;
}
int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
reg = RREG32(mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
enum BACO_STATE cur_state;
ci_baco_get_state(hwmgr, &cur_state);
smu7_baco_get_state(hwmgr, &cur_state);
if (cur_state == state)
/* aisc already in the target state */

5
drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
View File

@ -22,11 +22,8 @@
*/
#ifndef __CI_BACO_H__
#define __CI_BACO_H__
#include "hwmgr.h"
#include "common_baco.h"
#include "smu7_baco.h"
extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
#endif

34
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
View File

@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
{ CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
};
int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
*cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
return 0;
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
*cap = true;
return 0;
}
int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
reg = RREG32(mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
enum BACO_STATE cur_state;
fiji_baco_get_state(hwmgr, &cur_state);
smu7_baco_get_state(hwmgr, &cur_state);
if (cur_state == state)
/* aisc already in the target state */

5
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
View File

@ -22,11 +22,8 @@
*/
#ifndef __FIJI_BACO_H__
#define __FIJI_BACO_H__
#include "hwmgr.h"
#include "common_baco.h"
#include "smu7_baco.h"
extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
#endif

34
drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
View File

@ -178,43 +178,11 @@ static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
};
int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
*cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
return 0;
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
*cap = true;
return 0;
}
int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
reg = RREG32(mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
enum BACO_STATE cur_state;
polaris_baco_get_state(hwmgr, &cur_state);
smu7_baco_get_state(hwmgr, &cur_state);
if (cur_state == state)
/* aisc already in the target state */

5
drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
View File

@ -22,11 +22,8 @@
*/
#ifndef __POLARIS_BACO_H__
#define __POLARIS_BACO_H__
#include "hwmgr.h"
#include "common_baco.h"
#include "smu7_baco.h"
extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
#endif

91
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c Normal file
View File

@ -0,0 +1,91 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "amdgpu.h"
#include "smu7_baco.h"
#include "tonga_baco.h"
#include "fiji_baco.h"
#include "polaris_baco.h"
#include "ci_baco.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
*cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
return 0;
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
*cap = true;
return 0;
}
int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
reg = RREG32(mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
switch (adev->asic_type) {
case CHIP_TOPAZ:
case CHIP_TONGA:
return tonga_baco_set_state(hwmgr, state);
case CHIP_FIJI:
return fiji_baco_set_state(hwmgr, state);
case CHIP_POLARIS10:
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
return polaris_baco_set_state(hwmgr, state);
#ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_BONAIRE:
case CHIP_HAWAII:
return ci_baco_set_state(hwmgr, state);
#endif
default:
return -EINVAL;
}
}

32
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU7_BACO_H__
#define __SMU7_BACO_H__
#include "hwmgr.h"
#include "common_baco.h"
extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
#endif

34
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
View File

@ -182,43 +182,11 @@ static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
};
int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
*cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
return 0;
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
*cap = true;
return 0;
}
int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;
reg = RREG32(mmBACO_CNTL);
if (reg & BACO_CNTL__BACO_MODE_MASK)
/* gfx has already entered BACO state */
*state = BACO_STATE_IN;
else
*state = BACO_STATE_OUT;
return 0;
}
int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
{
enum BACO_STATE cur_state;
tonga_baco_get_state(hwmgr, &cur_state);
smu7_baco_get_state(hwmgr, &cur_state);
if (cur_state == state)
/* aisc already in the target state */

5
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
View File

@ -22,11 +22,8 @@
*/
#ifndef __TONGA_BACO_H__
#define __TONGA_BACO_H__
#include "hwmgr.h"
#include "common_baco.h"
#include "smu7_baco.h"
extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
#endif