forked from Minki/linux
staging: dwc2: make dwc2_core_params documentation more complete
Some of the defaults were missing or unclear. In particular, I suspect the defaults were documented assuming there were still module parameters and taking the default module parameters into account. Now, the defaults are the values that will get chosen when the params passed to dwc2_hcd_init are all -1. Signed-off-by: Matthijs Kooijman <matthijs@stdin.nl> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matthijs Kooijman
Greg Kroah-Hartman
parent
de4a193193
commit
91121c103a
@ -68,19 +68,18 @@ enum dwc2_lx_state {
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/**
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* struct dwc2_core_params - Parameters for configuring the core
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*
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* @otg_cap: Specifies the OTG capabilities. The driver will
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* automatically detect the value for this parameter if
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* none is specified.
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* 0 - HNP and SRP capable (default)
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* @otg_cap: Specifies the OTG capabilities.
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* 0 - HNP and SRP capable
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* 1 - SRP Only capable
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* 2 - No HNP/SRP capable
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* 2 - No HNP/SRP capable (always available)
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* Defaults to best available option (0, 1, then 2)
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* @otg_ver: OTG version supported
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* 0 - 1.3
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* 0 - 1.3 (default)
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* 1 - 2.0
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* @dma_enable: Specifies whether to use slave or DMA mode for accessing
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* the data FIFOs. The driver will automatically detect the
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* value for this parameter if none is specified.
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* 0 - Slave
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* 0 - Slave (always available)
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* 1 - DMA (default, if available)
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* @dma_desc_enable: When DMA mode is enabled, specifies whether to use
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* address DMA mode or descriptor DMA mode for accessing
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@ -91,29 +90,47 @@ enum dwc2_lx_state {
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* @speed: Specifies the maximum speed of operation in host and
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* device mode. The actual speed depends on the speed of
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* the attached device and the value of phy_type.
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* 0 - High Speed (default)
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* 0 - High Speed
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* (default when phy_type is UTMI+ or ULPI)
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* 1 - Full Speed
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* (default when phy_type is Full Speed)
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* @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
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* 1 - Allow dynamic FIFO sizing (default)
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* 1 - Allow dynamic FIFO sizing (default, if available)
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* @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
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* are enabled
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* @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
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* dynamic FIFO sizing is enabled
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* 16 to 32768 (default 1024)
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
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* in host mode when dynamic FIFO sizing is enabled
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* 16 to 32768 (default 1024)
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
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* host mode when dynamic FIFO sizing is enabled
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* 16 to 32768 (default 1024)
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @max_transfer_size: The maximum transfer size supported, in bytes
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* 2047 to 65,535 (default 65,535)
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* 2047 to 65,535
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* Actual maximum value is autodetected and also
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* the default.
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* @max_packet_count: The maximum number of packets in a transfer
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* 15 to 511 (default 511)
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* 15 to 511
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* Actual maximum value is autodetected and also
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* the default.
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* @host_channels: The number of host channel registers to use
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* 1 to 16 (default 12)
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* 1 to 16
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* Actual maximum value is autodetected and also
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* the default.
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* @phy_type: Specifies the type of PHY interface to use. By default,
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* the driver will automatically detect the phy_type.
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* 0 - Full Speed Phy
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* 1 - UTMI+ Phy
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* 2 - ULPI Phy
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* Defaults to best available option (2, 1, then 0)
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* @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
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* is applicable for a phy_type of UTMI+ or ULPI. (For a
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* ULPI phy_type, this parameter indicates the data width
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@ -122,7 +139,7 @@ enum dwc2_lx_state {
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* parameter was set to "8 and 16 bits", meaning that the
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* core has been configured to work at either data path
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* width.
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* 8 or 16 (default 16)
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* 8 or 16 (default 16 if available)
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* @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
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* data rate. This parameter is only applicable if phy_type
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* is ULPI.
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@ -132,35 +149,51 @@ enum dwc2_lx_state {
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* data bus
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* @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
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* external supply to drive the VBus
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* 0 - Internal supply (default)
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* 1 - External supply
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* @i2c_enable: Specifies whether to use the I2Cinterface for a full
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* speed PHY. This parameter is only applicable if phy_type
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* is FS.
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* 0 - No (default)
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* 1 - Yes
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* @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only
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* @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
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* 0 - No (default)
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* 1 - Yes
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* @host_support_fs_ls_low_power: Specifies whether low power mode is supported
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* when attached to a Full Speed or Low Speed device in
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* host mode.
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* 0 - Don't support low power mode (default)
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* 1 - Support low power mode
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* @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
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* when connected to a Low Speed device in host mode. This
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* parameter is applicable only if
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* host_support_fs_ls_low_power is enabled. If phy_type is
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* set to FS then defaults to 6 MHZ otherwise 48 MHZ.
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* when connected to a Low Speed device in host
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* mode. This parameter is applicable only if
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* host_support_fs_ls_low_power is enabled.
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* 0 - 48 MHz
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* (default when phy_type is UTMI+ or ULPI)
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* 1 - 6 MHz
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* @ts_dline: True to enable Term Select Dline pulsing
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* @reload_ctl: True to allow dynamic reloading of HFIR register during
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* runtime
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* (default when phy_type is Full Speed)
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* @ts_dline: Enable Term Select Dline pulsing
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* 0 - No (default)
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* 1 - Yes
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* @reload_ctl: Allow dynamic reloading of HFIR register during runtime
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* 0 - No (default for core < 2.92a)
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* 1 - Yes (default for core >= 2.92a)
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* @ahbcfg: This field allows the default value of the GAHBCFG
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* register to be overridden
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* -1 - GAHBCFG value will not be overridden
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* -1 - GAHBCFG value will be set to 0x06
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* (INCR4, default)
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* all others - GAHBCFG value will be overridden with
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* this value
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* Not all bits can be controlled like this, the
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* bits defined by GAHBCFG_CTRL_MASK are controlled
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* by the driver and are ignored in this
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* configuration value.
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*
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* The following parameters may be specified when starting the module. These
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* parameters define how the DWC_otg controller should be configured.
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* parameters define how the DWC_otg controller should be configured. A
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* value of -1 (or any other out of range value) for any parameter means
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* to read the value from hardware (if possible) or use the builtin
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* default described above.
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*/
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struct dwc2_core_params {
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/*
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