forked from Minki/linux
Merge branch 'for-next/errata' into for-next/core
Rework of the workaround for Cortex-A76 erratum 1463225 to fit in better with the ongoing exception entry cleanups and changes to the detection code for Cortex-A55 erratum 1024718 since it applies to all revisions of the silicon. * for-next/errata: arm64: entry: consolidate Cortex-A76 erratum 1463225 workaround arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
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commit
90eb8c9d94
@ -522,7 +522,7 @@ config ARM64_ERRATUM_1024718
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help
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This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
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Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
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Affected Cortex-A55 cores (all revisions) could cause incorrect
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update of the hardware dirty bit when the DBM/AP bits are updated
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without a break-before-make. The workaround is to disable the usage
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of hardware DBM locally on the affected cores. CPUs not affected by
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@ -107,8 +107,6 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
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}
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static bool
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has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
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int scope)
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@ -1506,7 +1506,7 @@ static bool cpu_has_broken_dbm(void)
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/* List of CPUs which have broken DBM support. */
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static const struct midr_range cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_1024718
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MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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/* Kryo4xx Silver (rdpe => r1p0) */
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MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
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#endif
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@ -109,6 +109,55 @@ asmlinkage void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
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exit_to_kernel_mode(regs);
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}
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static void cortex_a76_erratum_1463225_svc_handler(void)
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{
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u32 reg, val;
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if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
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return;
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if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
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return;
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
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reg = read_sysreg(mdscr_el1);
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val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
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write_sysreg(val, mdscr_el1);
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asm volatile("msr daifclr, #8");
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isb();
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/* We will have taken a single-step exception by this point */
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write_sysreg(reg, mdscr_el1);
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
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}
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static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
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return false;
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/*
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* We've taken a dummy step exception from the kernel to ensure
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* that interrupts are re-enabled on the syscall path. Return back
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* to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
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* masked so that we can safely restore the mdscr and get on with
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* handling the syscall.
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*/
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regs->pstate |= PSR_D_BIT;
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return true;
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}
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#else /* CONFIG_ARM64_ERRATUM_1463225 */
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static void cortex_a76_erratum_1463225_svc_handler(void) { }
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static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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return false;
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}
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#endif /* CONFIG_ARM64_ERRATUM_1463225 */
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static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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@ -186,7 +235,8 @@ static void noinstr el1_dbg(struct pt_regs *regs, unsigned long esr)
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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arm64_enter_el1_dbg(regs);
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do_debug_exception(far, esr, regs);
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if (!cortex_a76_erratum_1463225_debug_handler(regs))
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do_debug_exception(far, esr, regs);
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arm64_exit_el1_dbg(regs);
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}
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@ -362,6 +412,7 @@ static void noinstr el0_svc(struct pt_regs *regs)
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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enter_from_user_mode();
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cortex_a76_erratum_1463225_svc_handler();
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do_el0_svc(regs);
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}
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@ -439,6 +490,7 @@ static void noinstr el0_svc_compat(struct pt_regs *regs)
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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enter_from_user_mode();
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cortex_a76_erratum_1463225_svc_handler();
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do_el0_svc_compat(regs);
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}
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@ -65,35 +65,6 @@ static inline bool has_syscall_work(unsigned long flags)
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int syscall_trace_enter(struct pt_regs *regs);
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void syscall_trace_exit(struct pt_regs *regs);
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static void cortex_a76_erratum_1463225_svc_handler(void)
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{
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u32 reg, val;
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if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
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return;
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if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
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return;
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
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reg = read_sysreg(mdscr_el1);
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val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
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write_sysreg(val, mdscr_el1);
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asm volatile("msr daifclr, #8");
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isb();
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/* We will have taken a single-step exception by this point */
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write_sysreg(reg, mdscr_el1);
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
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}
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#else
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static void cortex_a76_erratum_1463225_svc_handler(void) { }
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#endif /* CONFIG_ARM64_ERRATUM_1463225 */
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static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
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const syscall_fn_t syscall_table[])
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{
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@ -120,7 +91,6 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
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* (Similarly for HVC and SMC elsewhere.)
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*/
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cortex_a76_erratum_1463225_svc_handler();
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local_daif_restore(DAIF_PROCCTX);
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if (flags & _TIF_MTE_ASYNC_FAULT) {
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@ -874,44 +874,12 @@ static void debug_exception_exit(struct pt_regs *regs)
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}
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NOKPROBE_SYMBOL(debug_exception_exit);
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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if (user_mode(regs))
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return 0;
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if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
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return 0;
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/*
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* We've taken a dummy step exception from the kernel to ensure
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* that interrupts are re-enabled on the syscall path. Return back
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* to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
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* masked so that we can safely restore the mdscr and get on with
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* handling the syscall.
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*/
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regs->pstate |= PSR_D_BIT;
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return 1;
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}
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#else
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static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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return 0;
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}
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#endif /* CONFIG_ARM64_ERRATUM_1463225 */
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NOKPROBE_SYMBOL(cortex_a76_erratum_1463225_debug_handler);
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void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr,
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struct pt_regs *regs)
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{
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const struct fault_info *inf = esr_to_debug_fault_info(esr);
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unsigned long pc = instruction_pointer(regs);
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if (cortex_a76_erratum_1463225_debug_handler(regs))
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return;
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debug_exception_enter(regs);
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if (user_mode(regs) && !is_ttbr0_addr(pc))
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