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ARC fixes for 4.14-rc7

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- Fixes for HSDK platform
  - module build error for !LLSC config
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Merge tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta:

 - Fixes for HSDK platform

 - module build error for !LLSC config

* tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: unbork module link errors with !CONFIG_ARC_HAS_LLSC
  ARC: [plat-hsdk] Increase SDIO CIU frequency to 50000000Hz
  ARC: [plat-hsdk] select CONFIG_RESET_HSDK from Kconfig
This commit is contained in:
Linus Torvalds 2017-10-27 20:38:47 -07:00
commit 90e6872061
5 changed files with 22 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arc/boot/dts/hsdk.dts
View File

@ -137,14 +137,15 @@
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. Due to its
* unexpected default value (it should devide by 1
* but it devides by 8) SDIO IP uses wrong clock and
* unexpected default value (it should divide by 1
* but it divides by 8) SDIO IP uses wrong clock and
* works unstable (see STAR 9001204800)
* We switched to the minimum possible value of the
* divisor (div-by-2) in HSDK platform code.
* So add temporary fix and change clock frequency
* from 100000000 to 12500000 Hz until we fix dw sdio
* driver itself.
* to 50000000 Hz until we fix dw sdio driver itself.
*/
clock-frequency = <12500000>;
clock-frequency = <50000000>;
#clock-cells = <0>;
};

1
arch/arc/configs/hsdk_defconfig
View File

@ -63,7 +63,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_HSDK=y
CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y

5
arch/arc/kernel/smp.c
View File

@ -23,6 +23,8 @@
#include <linux/cpumask.h>
#include <linux/reboot.h>
#include <linux/irqdomain.h>
#include <linux/export.h>
#include <asm/processor.h>
#include <asm/setup.h>
#include <asm/mach_desc.h>
@ -30,6 +32,9 @@
#ifndef CONFIG_ARC_HAS_LLSC
arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
EXPORT_SYMBOL_GPL(smp_atomic_ops_lock);
EXPORT_SYMBOL_GPL(smp_bitops_lock);
#endif
struct plat_smp_ops __weak plat_smp_ops;

1
arch/arc/plat-hsdk/Kconfig
View File

@ -8,3 +8,4 @@
menuconfig ARC_SOC_HSDK
bool "ARC HS Development Kit SOC"
select CLK_HSDK
select RESET_HSDK

10
arch/arc/plat-hsdk/platform.c
View File

@ -74,6 +74,10 @@ static void __init hsdk_set_cpu_freq_1ghz(void)
pr_err("Failed to setup CPU frequency to 1GHz!");
}
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
static void __init hsdk_init_early(void)
{
/*
@ -89,6 +93,12 @@ static void __init hsdk_init_early(void)
/* Really apply settings made above */
writel(1, (void __iomem *) CREG_PAE_UPDATE);
/*
* Switch SDIO external ciu clock divider from default div-by-8 to
* minimum possible div-by-2.
*/
iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
/*
* Setup CPU frequency to 1GHz.
* TODO: remove it after smart hsdk pll driver will be introduced.