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PCI: dwc: Remove read_dbi2 code

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The DBI2 appears to be write-only and there's no read accesses in the code
anyways, so let's remove all the read_dbi2 related code.

Link: https://lore.kernel.org/r/20200821035420.380495-33-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
This commit is contained in:
Rob Herring
2020-08-20 21:54:12 -06:00
committed by Lorenzo Pieralisi
parent 84667a416d
commit 903d69f83c
3 changed files with 0 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/pci/controller/dwc/pci-keystone.c
View File

@@ -881,18 +881,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
return 0; return 0;
} }
static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base,
u32 reg, size_t size)
{
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
u32 val;
ks_pcie_set_dbi_mode(ks_pcie);
dw_pcie_read(base + reg, size, &val);
ks_pcie_clear_dbi_mode(ks_pcie);
return val;
}
static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base,
u32 reg, size_t size, u32 val) u32 reg, size_t size, u32 val)
{ {
@@ -907,7 +895,6 @@ static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
.start_link = ks_pcie_start_link, .start_link = ks_pcie_start_link,
.stop_link = ks_pcie_stop_link, .stop_link = ks_pcie_stop_link,
.link_up = ks_pcie_link_up, .link_up = ks_pcie_link_up,
.read_dbi2 = ks_pcie_am654_read_dbi2,
.write_dbi2 = ks_pcie_am654_write_dbi2, .write_dbi2 = ks_pcie_am654_write_dbi2,
}; };

15
drivers/pci/controller/dwc/pcie-designware.c
View File

@@ -166,21 +166,6 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
} }
EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size)
{
int ret;
u32 val;
if (pci->ops->read_dbi2)
return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size);
ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val);
if (ret)
dev_err(pci->dev, "read DBI address failed\n");
return val;
}
void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
{ {
int ret; int ret;

8
drivers/pci/controller/dwc/pcie-designware.h
View File

@@ -232,8 +232,6 @@ struct dw_pcie_ops {
size_t size); size_t size);
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size, u32 val); size_t size, u32 val);
u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size);
void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
size_t size, u32 val); size_t size, u32 val);
int (*link_up)(struct dw_pcie *pcie); int (*link_up)(struct dw_pcie *pcie);
@@ -269,7 +267,6 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val);
u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);
void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size);
void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size); u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size);
void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
@@ -322,11 +319,6 @@ static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
dw_pcie_write_dbi2(pci, reg, 0x4, val); dw_pcie_write_dbi2(pci, reg, 0x4, val);
} }
static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
{
return dw_pcie_read_dbi2(pci, reg, 0x4);
}
static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
{ {
dw_pcie_write_atu(pci, reg, 0x4, val); dw_pcie_write_atu(pci, reg, 0x4, val);