forked from Minki/linux
gpio: davinci: Remove gpio2regs function
gpio2regs is written making an assumption that driver supports only one instance of gpio controller. Removing this and adding a generic array so as to support multiple instances of gpio controllers. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -43,25 +43,7 @@ typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
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#define MAX_LABEL_SIZE 20
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static void __iomem *gpio_base;
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static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
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{
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void __iomem *ptr;
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if (gpio < 32 * 1)
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ptr = gpio_base + 0x10;
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else if (gpio < 32 * 2)
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ptr = gpio_base + 0x38;
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else if (gpio < 32 * 3)
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ptr = gpio_base + 0x60;
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else if (gpio < 32 * 4)
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ptr = gpio_base + 0x88;
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else if (gpio < 32 * 5)
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ptr = gpio_base + 0xb0;
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else
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ptr = NULL;
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return ptr;
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}
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static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
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static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
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{
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@ -262,7 +244,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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#endif
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spin_lock_init(&chips[i].lock);
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regs = gpio2regs(base);
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regs = gpio_base + offset_array[i];
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if (!regs)
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return -ENXIO;
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chips[i].regs = regs;
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@ -417,7 +399,9 @@ static int
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davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
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struct davinci_gpio_controller *chips =
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(struct davinci_gpio_controller *)d->host_data;
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struct davinci_gpio_regs __iomem *g = chips[hw / 32].regs;
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irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
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"davinci_gpio");
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@ -554,7 +538,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
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irq_chip->irq_set_type = gpio_irq_type_unbanked;
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/* default trigger: both edges */
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g = gpio2regs(0);
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g = chips[0].regs;
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writel_relaxed(~0, &g->set_falling);
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writel_relaxed(~0, &g->set_rising);
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@ -573,8 +557,11 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
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* then chain through our own handler.
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*/
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for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
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/* disabled by default, enabled only as needed */
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g = gpio2regs(gpio);
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/* disabled by default, enabled only as needed
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* There are register sets for 32 GPIOs. 2 banks of 16
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* GPIOs are covered by each set of registers hence divide by 2
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*/
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g = chips[bank / 2].regs;
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writel_relaxed(~0, &g->clr_falling);
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writel_relaxed(~0, &g->clr_rising);
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