forked from Minki/linux
mtd: nand: pxa3xx-nand: switch to dmaengine
Now pxa architecture has a dmaengine driver, remove the access to direct dma registers in favor of the more generic dmaengine code. This should be also applicable for mmp and orion, provided they work in device-tree environment. This patch also removes the previous hack which was necessary to make the driver work in a devicetree environment. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> [Brian: fixup use of 'enum dma_transfer_direction'] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Robert Jarzmik
Brian Norris
parent
e1305df128
commit
8f5ba31aa5
@ -15,7 +15,9 @@
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma/pxa-dma.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/mtd/mtd.h>
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@ -33,10 +35,6 @@
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#define ARCH_HAS_DMA
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#endif
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#ifdef ARCH_HAS_DMA
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#include <mach/dma.h>
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#endif
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#include <linux/platform_data/mtd-nand-pxa3xx.h>
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#define CHIP_DELAY_TIMEOUT msecs_to_jiffies(200)
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@ -201,6 +199,10 @@ struct pxa3xx_nand_info {
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unsigned int oob_buff_pos;
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/* DMA information */
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struct scatterlist sg;
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enum dma_data_direction dma_dir;
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struct dma_chan *dma_chan;
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dma_cookie_t dma_cookie;
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int drcmr_dat;
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int drcmr_cmd;
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@ -208,8 +210,6 @@ struct pxa3xx_nand_info {
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unsigned char *oob_buff;
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dma_addr_t data_buff_phys;
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int data_dma_ch;
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struct pxa_dma_desc *data_desc;
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dma_addr_t data_desc_addr;
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struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
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unsigned int state;
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@ -492,6 +492,9 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
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ndcr &= ~NDCR_ND_RUN;
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nand_writel(info, NDCR, ndcr);
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}
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if (info->dma_chan)
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dmaengine_terminate_all(info->dma_chan);
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/* clear status bits */
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nand_writel(info, NDSR, NDSR_MASK);
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}
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@ -583,58 +586,62 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
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info->data_size -= do_bytes;
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}
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#ifdef ARCH_HAS_DMA
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static void pxa3xx_nand_data_dma_irq(void *data)
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{
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struct pxa3xx_nand_info *info = data;
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struct dma_tx_state state;
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enum dma_status status;
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status = dmaengine_tx_status(info->dma_chan, info->dma_cookie, &state);
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if (likely(status == DMA_COMPLETE)) {
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info->state = STATE_DMA_DONE;
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} else {
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dev_err(&info->pdev->dev, "DMA error on data channel\n");
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info->retcode = ERR_DMABUSERR;
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}
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dma_unmap_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir);
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nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
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enable_int(info, NDCR_INT_MASK);
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}
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static void start_data_dma(struct pxa3xx_nand_info *info)
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{
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struct pxa_dma_desc *desc = info->data_desc;
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int dma_len = ALIGN(info->data_size + info->oob_size, 32);
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desc->ddadr = DDADR_STOP;
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desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
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enum dma_transfer_direction direction;
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struct dma_async_tx_descriptor *tx;
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switch (info->state) {
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case STATE_DMA_WRITING:
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desc->dsadr = info->data_buff_phys;
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desc->dtadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
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info->dma_dir = DMA_TO_DEVICE;
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direction = DMA_MEM_TO_DEV;
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break;
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case STATE_DMA_READING:
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desc->dtadr = info->data_buff_phys;
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desc->dsadr = info->mmio_phys + NDDB;
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desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
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info->dma_dir = DMA_FROM_DEVICE;
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direction = DMA_DEV_TO_MEM;
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break;
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default:
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dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
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info->state);
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BUG();
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}
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info->sg.length = info->data_size +
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(info->oob_size ? info->spare_size + info->ecc_size : 0);
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dma_map_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir);
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DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
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DDADR(info->data_dma_ch) = info->data_desc_addr;
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DCSR(info->data_dma_ch) |= DCSR_RUN;
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tx = dmaengine_prep_slave_sg(info->dma_chan, &info->sg, 1, direction,
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DMA_PREP_INTERRUPT);
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if (!tx) {
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dev_err(&info->pdev->dev, "prep_slave_sg() failed\n");
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return;
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}
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static void pxa3xx_nand_data_dma_irq(int channel, void *data)
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{
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struct pxa3xx_nand_info *info = data;
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uint32_t dcsr;
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dcsr = DCSR(channel);
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DCSR(channel) = dcsr;
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if (dcsr & DCSR_BUSERR) {
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info->retcode = ERR_DMABUSERR;
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tx->callback = pxa3xx_nand_data_dma_irq;
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tx->callback_param = info;
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info->dma_cookie = dmaengine_submit(tx);
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dma_async_issue_pending(info->dma_chan);
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dev_dbg(&info->pdev->dev, "%s(dir=%d cookie=%x size=%u)\n",
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__func__, direction, info->dma_cookie, info->sg.length);
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}
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info->state = STATE_DMA_DONE;
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enable_int(info, NDCR_INT_MASK);
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nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
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}
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#else
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static void start_data_dma(struct pxa3xx_nand_info *info)
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{}
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#endif
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static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data)
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{
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struct pxa3xx_nand_info *info = data;
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@ -1319,36 +1326,50 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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return 0;
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}
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#ifdef ARCH_HAS_DMA
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static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
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{
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struct platform_device *pdev = info->pdev;
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int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc);
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struct dma_slave_config config;
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dma_cap_mask_t mask;
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struct pxad_param param;
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int ret;
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if (use_dma == 0) {
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info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
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if (info->data_buff == NULL)
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return -ENOMEM;
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if (use_dma == 0)
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return 0;
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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sg_init_one(&info->sg, info->data_buff, info->buf_size);
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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param.prio = PXAD_PRIO_LOWEST;
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param.drcmr = info->drcmr_dat;
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info->dma_chan = dma_request_slave_channel_compat(mask, pxad_filter_fn,
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¶m, &pdev->dev,
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"data");
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if (!info->dma_chan) {
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dev_err(&pdev->dev, "unable to request data dma channel\n");
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return -ENODEV;
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}
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info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size,
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&info->data_buff_phys, GFP_KERNEL);
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if (info->data_buff == NULL) {
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dev_err(&pdev->dev, "failed to allocate dma buffer\n");
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return -ENOMEM;
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}
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info->data_desc = (void *)info->data_buff + data_desc_offset;
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info->data_desc_addr = info->data_buff_phys + data_desc_offset;
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info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
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pxa3xx_nand_data_dma_irq, info);
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if (info->data_dma_ch < 0) {
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dev_err(&pdev->dev, "failed to request data dma\n");
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dma_free_coherent(&pdev->dev, info->buf_size,
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info->data_buff, info->data_buff_phys);
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return info->data_dma_ch;
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memset(&config, 0, sizeof(config));
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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config.src_addr = info->mmio_phys + NDDB;
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config.dst_addr = info->mmio_phys + NDDB;
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config.src_maxburst = 32;
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config.dst_maxburst = 32;
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ret = dmaengine_slave_config(info->dma_chan, &config);
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if (ret < 0) {
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dev_err(&info->pdev->dev,
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"dma channel configuration failed: %d\n",
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ret);
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return ret;
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}
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/*
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@ -1361,29 +1382,12 @@ static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
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static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
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{
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struct platform_device *pdev = info->pdev;
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if (info->use_dma) {
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pxa_free_dma(info->data_dma_ch);
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dma_free_coherent(&pdev->dev, info->buf_size,
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info->data_buff, info->data_buff_phys);
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} else {
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dmaengine_terminate_all(info->dma_chan);
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dma_release_channel(info->dma_chan);
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}
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kfree(info->data_buff);
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}
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}
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#else
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static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
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{
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info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
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if (info->data_buff == NULL)
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return -ENOMEM;
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return 0;
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}
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static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
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{
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kfree(info->data_buff);
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}
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#endif
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static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
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{
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@ -1683,16 +1687,6 @@ static int alloc_nand_resource(struct platform_device *pdev)
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return ret;
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if (use_dma) {
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/*
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* This is a dirty hack to make this driver work from
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* devicetree bindings. It can be removed once we have
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* a prober DMA controller framework for DT.
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*/
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if (pdev->dev.of_node &&
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of_machine_is_compatible("marvell,pxa3xx")) {
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info->drcmr_dat = 97;
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info->drcmr_cmd = 99;
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} else {
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r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (r == NULL) {
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dev_err(&pdev->dev,
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@ -1711,7 +1705,6 @@ static int alloc_nand_resource(struct platform_device *pdev)
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}
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info->drcmr_cmd = r->start;
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}
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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@ -1821,15 +1814,16 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
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struct pxa3xx_nand_platform_data *pdata;
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struct mtd_part_parser_data ppdata = {};
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struct pxa3xx_nand_info *info;
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int ret, cs, probe_success;
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int ret, cs, probe_success, dma_available;
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#ifndef ARCH_HAS_DMA
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if (use_dma) {
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dma_available = IS_ENABLED(CONFIG_ARM) &&
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(IS_ENABLED(CONFIG_ARCH_PXA) || IS_ENABLED(CONFIG_ARCH_MMP));
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if (use_dma && !dma_available) {
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use_dma = 0;
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dev_warn(&pdev->dev,
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"This platform can't do DMA on this device\n");
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}
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#endif
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ret = pxa3xx_nand_probe_dt(pdev);
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if (ret)
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return ret;
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