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drm/amd/powerplay: move od_default_setting callback to asic file

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the set default od_setting is asic related function,
so move thic code to vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kevin Wang 2019-05-21 15:37:24 +08:00 committed by Alex Deucher
parent a259714bb2
commit 8f30a16d3a
4 changed files with 43 additions and 50 deletions
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2
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -901,7 +901,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
ret = smu_set_od8_default_settings(smu, initialize);
ret = smu_set_default_od_settings(smu, initialize);
if (ret)
return ret;

7
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -609,6 +609,7 @@ struct pptable_funcs {
uint32_t *value);
int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
};
struct smu_funcs
@ -672,8 +673,6 @@ struct smu_funcs
int (*notify_smu_enable_pwe)(struct smu_context *smu);
int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
int (*set_od8_default_settings)(struct smu_context *smu,
bool initialize);
int (*conv_power_profile_to_pplib_workload)(int power_profile);
int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
uint32_t (*get_fan_control_mode)(struct smu_context *smu);
@ -733,8 +732,8 @@ struct smu_funcs
((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
#define smu_init_max_sustainable_clocks(smu) \
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_od8_default_settings(smu, initialize) \
((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu), (initialize)) : 0)
#define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
#define smu_get_current_rpm(smu, speed) \
((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
#define smu_set_fan_speed_rpm(smu, speed) \

44
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -1357,49 +1357,6 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
return ret;
}
static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
bool initialize)
{
struct smu_table_context *table_context = &smu->smu_table;
struct smu_table *table = &table_context->tables[SMU_TABLE_OVERDRIVE];
int ret;
/**
* TODO: Enable overdrive for navi10, that replies on smc/pptable
* support.
*/
if (smu->adev->asic_type == CHIP_NAVI10)
return 0;
if (initialize) {
if (table_context->overdrive_table)
return -EINVAL;
table_context->overdrive_table = kzalloc(table->size, GFP_KERNEL);
if (!table_context->overdrive_table)
return -ENOMEM;
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, false);
if (ret) {
pr_err("Failed to export over drive table!\n");
return ret;
}
smu_set_default_od8_settings(smu);
}
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, true);
if (ret) {
pr_err("Failed to import over drive table!\n");
return ret;
}
return 0;
}
static int smu_v11_0_get_current_rpm(struct smu_context *smu,
uint32_t *current_rpm)
{
@ -1686,7 +1643,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
.set_od8_default_settings = smu_v11_0_set_od8_default_settings,
.get_current_rpm = smu_v11_0_get_current_rpm,
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,

40
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -1689,6 +1689,44 @@ static int vega20_get_metrics_table(struct smu_context *smu,
return ret;
}
static int vega20_set_default_od_settings(struct smu_context *smu,
bool initialize)
{
struct smu_table_context *table_context = &smu->smu_table;
int ret;
if (initialize) {
if (table_context->overdrive_table)
return -EINVAL;
table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
if (!table_context->overdrive_table)
return -ENOMEM;
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, false);
if (ret) {
pr_err("Failed to export over drive table!\n");
return ret;
}
ret = vega20_set_default_od8_setttings(smu);
if (ret)
return ret;
}
ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, true);
if (ret) {
pr_err("Failed to import over drive table!\n");
return ret;
}
return 0;
}
static int vega20_get_od_percentage(struct smu_context *smu,
enum smu_clk_type clk_type)
{
@ -3228,11 +3266,11 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.print_clk_levels = vega20_print_clk_levels,
.force_clk_levels = vega20_force_clk_levels,
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
.set_default_od8_settings = vega20_set_default_od8_setttings,
.get_od_percentage = vega20_get_od_percentage,
.get_power_profile_mode = vega20_get_power_profile_mode,
.set_power_profile_mode = vega20_set_power_profile_mode,
.set_od_percentage = vega20_set_od_percentage,
.set_default_od_settings = vega20_set_default_od_settings,
.od_edit_dpm_table = vega20_odn_edit_dpm_table,
.dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
.dpm_set_vce_enable = vega20_dpm_set_vce_enable,