drm/i915/guc/slpc: Add SLPC selftest
Tests that exercise the SLPC get/set frequency interfaces. Clamp_max will set max frequency to multiple levels and check that SLPC requests frequency lower than or equal to it. Clamp_min will set min frequency to different levels and check if SLPC requests are higher or equal to those levels. v2: Address review comments (Michal W) v3: Checkpatch() corrections v4: Remove unnecessary header file (Matthew Brost) v5: checkpatch() and define const for 50/3 (Matthew Brost) Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-14-vinay.belgaumkar@intel.com
This commit is contained in:
Vinay Belgaumkar
John Harrison
parent
41e5c17ebf
commit
8ee2c22782
@ -2333,4 +2333,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftest_rps.c"
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#include "selftest_slpc.c"
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#endif
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311
drivers/gpu/drm/i915/gt/selftest_slpc.c
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311
drivers/gpu/drm/i915/gt/selftest_slpc.c
Normal file
@ -0,0 +1,311 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#define NUM_STEPS 5
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#define H2G_DELAY 50000
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#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000)
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#define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \
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GEN9_FREQ_SCALER)
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static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
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{
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int ret;
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ret = intel_guc_slpc_set_min_freq(slpc, freq);
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if (ret)
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pr_err("Could not set min frequency to [%u]\n", freq);
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else /* Delay to ensure h2g completes */
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delay_for_h2g();
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return ret;
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}
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static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
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{
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int ret;
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ret = intel_guc_slpc_set_max_freq(slpc, freq);
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if (ret)
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pr_err("Could not set maximum frequency [%u]\n",
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freq);
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else /* Delay to ensure h2g completes */
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delay_for_h2g();
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return ret;
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}
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static int live_slpc_clamp_min(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_gt *gt = &i915->gt;
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struct intel_guc_slpc *slpc = >->uc.guc.slpc;
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struct intel_rps *rps = >->rps;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct igt_spinner spin;
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u32 slpc_min_freq, slpc_max_freq;
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int err = 0;
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if (!intel_uc_uses_guc_slpc(>->uc))
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return 0;
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if (igt_spinner_init(&spin, gt))
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return -ENOMEM;
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if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
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pr_err("Could not get SLPC max freq\n");
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return -EIO;
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}
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if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
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pr_err("Could not get SLPC min freq\n");
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return -EIO;
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}
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if (slpc_min_freq == slpc_max_freq) {
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pr_err("Min/Max are fused to the same value\n");
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return -EINVAL;
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}
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intel_gt_pm_wait_for_idle(gt);
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intel_gt_pm_get(gt);
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for_each_engine(engine, gt, id) {
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struct i915_request *rq;
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u32 step, min_freq, req_freq;
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u32 act_freq, max_act_freq;
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if (!intel_engine_can_store_dword(engine))
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continue;
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/* Go from min to max in 5 steps */
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step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
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max_act_freq = slpc_min_freq;
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for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
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min_freq += step) {
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err = slpc_set_min_freq(slpc, min_freq);
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if (err)
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break;
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st_engine_heartbeat_disable(engine);
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rq = igt_spinner_create_request(&spin,
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engine->kernel_context,
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MI_NOOP);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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st_engine_heartbeat_enable(engine);
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break;
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}
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i915_request_add(rq);
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if (!igt_wait_for_spinner(&spin, rq)) {
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pr_err("%s: Spinner did not start\n",
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engine->name);
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igt_spinner_end(&spin);
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st_engine_heartbeat_enable(engine);
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intel_gt_set_wedged(engine->gt);
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err = -EIO;
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break;
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}
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/* Wait for GuC to detect business and raise
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* requested frequency if necessary.
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*/
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delay_for_h2g();
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req_freq = intel_rps_read_punit_req_frequency(rps);
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/* GuC requests freq in multiples of 50/3 MHz */
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if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) {
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pr_err("SWReq is %d, should be at least %d\n", req_freq,
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min_freq - FREQUENCY_REQ_UNIT);
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igt_spinner_end(&spin);
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st_engine_heartbeat_enable(engine);
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err = -EINVAL;
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break;
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}
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act_freq = intel_rps_read_actual_frequency(rps);
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if (act_freq > max_act_freq)
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max_act_freq = act_freq;
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igt_spinner_end(&spin);
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st_engine_heartbeat_enable(engine);
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}
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pr_info("Max actual frequency for %s was %d\n",
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engine->name, max_act_freq);
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/* Actual frequency should rise above min */
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if (max_act_freq == slpc_min_freq) {
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pr_err("Actual freq did not rise above min\n");
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err = -EINVAL;
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}
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if (err)
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break;
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}
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/* Restore min/max frequencies */
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slpc_set_max_freq(slpc, slpc_max_freq);
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slpc_set_min_freq(slpc, slpc_min_freq);
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if (igt_flush_test(gt->i915))
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err = -EIO;
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intel_gt_pm_put(gt);
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igt_spinner_fini(&spin);
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intel_gt_pm_wait_for_idle(gt);
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return err;
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}
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static int live_slpc_clamp_max(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_gt *gt = &i915->gt;
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struct intel_guc_slpc *slpc;
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struct intel_rps *rps;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct igt_spinner spin;
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int err = 0;
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u32 slpc_min_freq, slpc_max_freq;
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slpc = >->uc.guc.slpc;
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rps = >->rps;
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if (!intel_uc_uses_guc_slpc(>->uc))
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return 0;
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if (igt_spinner_init(&spin, gt))
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return -ENOMEM;
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if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
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pr_err("Could not get SLPC max freq\n");
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return -EIO;
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}
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if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
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pr_err("Could not get SLPC min freq\n");
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return -EIO;
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}
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if (slpc_min_freq == slpc_max_freq) {
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pr_err("Min/Max are fused to the same value\n");
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return -EINVAL;
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}
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intel_gt_pm_wait_for_idle(gt);
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intel_gt_pm_get(gt);
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for_each_engine(engine, gt, id) {
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struct i915_request *rq;
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u32 max_freq, req_freq;
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u32 act_freq, max_act_freq;
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u32 step;
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if (!intel_engine_can_store_dword(engine))
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continue;
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/* Go from max to min in 5 steps */
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step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
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max_act_freq = slpc_min_freq;
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for (max_freq = slpc_max_freq; max_freq > slpc_min_freq;
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max_freq -= step) {
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err = slpc_set_max_freq(slpc, max_freq);
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if (err)
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break;
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st_engine_heartbeat_disable(engine);
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rq = igt_spinner_create_request(&spin,
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engine->kernel_context,
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MI_NOOP);
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if (IS_ERR(rq)) {
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st_engine_heartbeat_enable(engine);
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err = PTR_ERR(rq);
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break;
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}
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i915_request_add(rq);
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if (!igt_wait_for_spinner(&spin, rq)) {
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pr_err("%s: SLPC spinner did not start\n",
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engine->name);
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igt_spinner_end(&spin);
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st_engine_heartbeat_enable(engine);
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intel_gt_set_wedged(engine->gt);
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err = -EIO;
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break;
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}
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delay_for_h2g();
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/* Verify that SWREQ indeed was set to specific value */
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req_freq = intel_rps_read_punit_req_frequency(rps);
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/* GuC requests freq in multiples of 50/3 MHz */
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if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) {
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pr_err("SWReq is %d, should be at most %d\n", req_freq,
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max_freq + FREQUENCY_REQ_UNIT);
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igt_spinner_end(&spin);
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st_engine_heartbeat_enable(engine);
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err = -EINVAL;
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break;
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}
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act_freq = intel_rps_read_actual_frequency(rps);
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if (act_freq > max_act_freq)
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max_act_freq = act_freq;
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st_engine_heartbeat_enable(engine);
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igt_spinner_end(&spin);
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if (err)
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break;
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}
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pr_info("Max actual frequency for %s was %d\n",
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engine->name, max_act_freq);
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/* Actual frequency should rise above min */
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if (max_act_freq == slpc_min_freq) {
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pr_err("Actual freq did not rise above min\n");
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err = -EINVAL;
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}
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if (igt_flush_test(gt->i915)) {
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err = -EIO;
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break;
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}
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if (err)
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break;
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}
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/* Restore min/max freq */
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slpc_set_max_freq(slpc, slpc_max_freq);
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slpc_set_min_freq(slpc, slpc_min_freq);
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intel_gt_pm_put(gt);
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igt_spinner_fini(&spin);
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intel_gt_pm_wait_for_idle(gt);
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return err;
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}
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int intel_slpc_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_slpc_clamp_max),
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SUBTEST(live_slpc_clamp_min),
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};
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if (intel_gt_is_wedged(&i915->gt))
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return 0;
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return i915_live_subtests(tests, i915);
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}
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@ -47,5 +47,6 @@ selftest(hangcheck, intel_hangcheck_live_selftests)
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selftest(execlists, intel_execlists_live_selftests)
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selftest(ring_submission, intel_ring_submission_live_selftests)
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selftest(perf, i915_perf_live_selftests)
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selftest(slpc, intel_slpc_live_selftests)
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/* Here be dragons: keep last to run last! */
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selftest(late_gt_pm, intel_gt_pm_late_selftests)
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