drm/sti: missing first pixel column on HDMI display
VTG programing updated to fix the shift of one column observed on HDMI display. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
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8eba270311
@ -62,7 +62,7 @@
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#define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
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/* Delay introduced by the HDMI in nb of pixel */
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#define HDMI_DELAY (6)
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#define HDMI_DELAY (5)
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/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
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#define AWG_DELAY_HD (-9)
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@ -121,6 +121,32 @@ static void vtg_reset(struct sti_vtg *vtg)
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writel(1, vtg->regs + VTG_DRST_AUTOC);
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}
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static void vtg_set_output_window(void __iomem *regs,
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const struct drm_display_mode *mode)
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{
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u32 video_top_field_start;
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u32 video_top_field_stop;
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u32 video_bottom_field_start;
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u32 video_bottom_field_stop;
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u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
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u32 ystart = sti_vtg_get_line_number(*mode, 0);
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u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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/* Set output window to fit the display mode selected */
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video_top_field_start = (ystart << 16) | xstart;
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video_top_field_stop = (ystop << 16) | xstop;
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/* Only progressive supported for now */
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video_bottom_field_start = video_top_field_start;
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video_bottom_field_stop = video_top_field_stop;
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writel(video_top_field_start, regs + VTG_VID_TFO);
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writel(video_top_field_stop, regs + VTG_VID_TFS);
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writel(video_bottom_field_start, regs + VTG_VID_BFO);
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writel(video_bottom_field_stop, regs + VTG_VID_BFS);
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}
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static void vtg_set_mode(struct sti_vtg *vtg,
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int type, const struct drm_display_mode *mode)
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{
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@ -129,18 +155,14 @@ static void vtg_set_mode(struct sti_vtg *vtg,
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if (vtg->slave)
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vtg_set_mode(vtg->slave, VTG_TYPE_SLAVE_BY_EXT0, mode);
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/* Set the number of clock cycles per line */
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writel(mode->htotal, vtg->regs + VTG_CLKLN);
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/* Set Half Line Per Field (only progressive supported for now) */
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writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
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tmp = (mode->vtotal - mode->vsync_start + 1) << 16;
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tmp |= mode->htotal - mode->hsync_start;
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writel(tmp, vtg->regs + VTG_VID_TFO);
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writel(tmp, vtg->regs + VTG_VID_BFO);
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tmp = (mode->vdisplay + mode->vtotal - mode->vsync_start + 1) << 16;
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tmp |= mode->hdisplay + mode->htotal - mode->hsync_start;
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writel(tmp, vtg->regs + VTG_VID_TFS);
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writel(tmp, vtg->regs + VTG_VID_BFS);
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/* Program output window */
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vtg_set_output_window(vtg->regs, mode);
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/* prepare VTG set 1 for HDMI */
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tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;
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