clk: at91: clk-master: remove dead code

Commit facb87ad75 ("clk: at91: sama7g5: remove prescaler part of master
clock") removed the master clock's prescaler from clock tree of SAMA7G5
as it has been discovered that there is a hardware bug when trying to
change it at run-time (bug is described in description of
commit facb87ad75 ("clk: at91: sama7g5: remove prescaler part of master
clock")). This was previously changed at CPUFreq driver request. Thus, with
commit facb87ad75 ("clk: at91: sama7g5: remove prescaler part of master
clock") there is no need of code that handles run-time changes of master
clock's prescaler, thus remove this code.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea 2022-02-03 13:02:02 +02:00 committed by Nicolas Ferre
parent 1a944729d8
commit 8e842f02af
13 changed files with 18 additions and 134 deletions

View File

@ -143,8 +143,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
parent_names,
&at91rm9200_master_layout,
&rm9200_mck_characteristics,
&rm9200_mck_lock, CLK_SET_RATE_GATE,
INT_MIN);
&rm9200_mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -419,8 +419,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
parent_names,
&at91rm9200_master_layout,
data->mck_characteristics,
&at91sam9260_mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&at91sam9260_mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -154,8 +154,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
parent_names,
&at91rm9200_master_layout,
&mck_characteristics,
&at91sam9g45_mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&at91sam9g45_mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -181,8 +181,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
parent_names,
&at91sam9x5_master_layout,
&mck_characteristics,
&at91sam9n12_mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&at91sam9n12_mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -123,8 +123,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
parent_names,
&at91rm9200_master_layout,
&sam9rl_mck_characteristics,
&sam9rl_mck_lock, CLK_SET_RATE_GATE,
INT_MIN);
&sam9rl_mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -201,8 +201,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
parent_names,
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -374,85 +374,6 @@ static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
}
}
static int clk_master_pres_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_master *master = to_clk_master(hw);
struct clk_rate_request req_parent = *req;
const struct clk_master_characteristics *characteristics =
master->characteristics;
struct clk_hw *parent;
long best_rate = LONG_MIN, best_diff = LONG_MIN;
u32 pres;
int i;
if (master->chg_pid < 0)
return -EOPNOTSUPP;
parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
if (!parent)
return -EOPNOTSUPP;
for (i = 0; i <= MASTER_PRES_MAX; i++) {
if (characteristics->have_div3_pres && i == MASTER_PRES_MAX)
pres = 3;
else
pres = 1 << i;
req_parent.rate = req->rate * pres;
if (__clk_determine_rate(parent, &req_parent))
continue;
clk_sama7g5_master_best_diff(req, parent, req_parent.rate,
&best_diff, &best_rate, pres);
if (!best_diff)
break;
}
return 0;
}
static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_master *master = to_clk_master(hw);
unsigned long flags;
unsigned int pres, mckr, tmp;
int ret;
pres = DIV_ROUND_CLOSEST(parent_rate, rate);
if (pres > MASTER_PRES_MAX)
return -EINVAL;
else if (pres == 3)
pres = MASTER_PRES_MAX;
else if (pres)
pres = ffs(pres) - 1;
spin_lock_irqsave(master->lock, flags);
ret = regmap_read(master->regmap, master->layout->offset, &mckr);
if (ret)
goto unlock;
mckr &= master->layout->mask;
tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
if (pres == tmp)
goto unlock;
mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
mckr |= (pres << master->layout->pres_shift);
ret = regmap_write(master->regmap, master->layout->offset, mckr);
if (ret)
goto unlock;
while (!clk_master_ready(master))
cpu_relax();
unlock:
spin_unlock_irqrestore(master->lock, flags);
return ret;
}
static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@ -539,13 +460,6 @@ static void clk_master_pres_restore_context(struct clk_hw *hw)
pr_warn("MCKR PRES was not configured properly by firmware!\n");
}
static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
{
struct clk_master *master = to_clk_master(hw);
clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
}
static const struct clk_ops master_pres_ops = {
.prepare = clk_master_prepare,
.is_prepared = clk_master_is_prepared,
@ -555,25 +469,13 @@ static const struct clk_ops master_pres_ops = {
.restore_context = clk_master_pres_restore_context,
};
static const struct clk_ops master_pres_ops_chg = {
.prepare = clk_master_prepare,
.is_prepared = clk_master_is_prepared,
.determine_rate = clk_master_pres_determine_rate,
.recalc_rate = clk_master_pres_recalc_rate,
.get_parent = clk_master_pres_get_parent,
.set_rate = clk_master_pres_set_rate,
.save_context = clk_master_pres_save_context,
.restore_context = clk_master_pres_restore_context_chg,
};
static struct clk_hw * __init
at91_clk_register_master_internal(struct regmap *regmap,
const char *name, int num_parents,
const char **parent_names,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics,
const struct clk_ops *ops, spinlock_t *lock, u32 flags,
int chg_pid)
const struct clk_ops *ops, spinlock_t *lock, u32 flags)
{
struct clk_master *master;
struct clk_init_data init;
@ -599,7 +501,6 @@ at91_clk_register_master_internal(struct regmap *regmap,
master->layout = layout;
master->characteristics = characteristics;
master->regmap = regmap;
master->chg_pid = chg_pid;
master->lock = lock;
if (ops == &master_div_ops_chg) {
@ -628,19 +529,13 @@ at91_clk_register_master_pres(struct regmap *regmap,
const char **parent_names,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics,
spinlock_t *lock, u32 flags, int chg_pid)
spinlock_t *lock)
{
const struct clk_ops *ops;
if (flags & CLK_SET_RATE_GATE)
ops = &master_pres_ops;
else
ops = &master_pres_ops_chg;
return at91_clk_register_master_internal(regmap, name, num_parents,
parent_names, layout,
characteristics, ops,
lock, flags, chg_pid);
characteristics,
&master_pres_ops,
lock, CLK_SET_RATE_GATE);
}
struct clk_hw * __init
@ -661,7 +556,7 @@ at91_clk_register_master_div(struct regmap *regmap,
hw = at91_clk_register_master_internal(regmap, name, 1,
&parent_name, layout,
characteristics, ops,
lock, flags, -EINVAL);
lock, flags);
if (!IS_ERR(hw) && safe_div) {
master_div = to_clk_master(hw);

View File

@ -392,8 +392,7 @@ of_at91_clk_master_setup(struct device_node *np,
hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
parent_names, layout,
characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
characteristics, &mck_lock);
if (IS_ERR(hw))
goto out_free_characteristics;

View File

@ -175,7 +175,7 @@ at91_clk_register_master_pres(struct regmap *regmap, const char *name,
int num_parents, const char **parent_names,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics,
spinlock_t *lock, u32 flags, int chg_pid);
spinlock_t *lock);
struct clk_hw * __init
at91_clk_register_master_div(struct regmap *regmap, const char *name,

View File

@ -271,8 +271,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
parent_names[2] = "pllack_divck";
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3,
parent_names, &sam9x60_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -242,8 +242,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
parent_names,
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -175,8 +175,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
parent_names,
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;

View File

@ -190,8 +190,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
parent_names,
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, INT_MIN);
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;