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drm/i915: Fix LVDS panel fitting on Arrandale

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Arrandale has new window based method for panel fitting.
This one enables full screen aspect scaling on LVDS. It fixes
standard mode display failure on LVDS for Arrandale.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Zhenyu Wang 2009-09-19 14:54:09 +08:00 committed by Jesse Barnes
parent 730915d65f
commit 8dd81a381e
3 changed files with 24 additions and 3 deletions
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2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2000,6 +2000,8 @@
#define PF_ENABLE (1<<31) #define PF_ENABLE (1<<31)
#define PFA_WIN_SZ 0x68074 #define PFA_WIN_SZ 0x68074
#define PFB_WIN_SZ 0x68874 #define PFB_WIN_SZ 0x68874
#define PFA_WIN_POS 0x68070
#define PFB_WIN_POS 0x68870
/* legacy palette */ /* legacy palette */
#define LGC_PALETTE_A 0x4a000 #define LGC_PALETTE_A 0x4a000

14
drivers/gpu/drm/i915/intel_display.c
View File

@ -1391,6 +1391,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@ -1442,6 +1443,19 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
} }
} }
/* Enable panel fitting for LVDS */
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
temp = I915_READ(pf_ctl_reg);
I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
/* currently full aspect */
I915_WRITE(pf_win_pos, 0);
I915_WRITE(pf_win_size,
(dev_priv->panel_fixed_mode->hdisplay << 16) |
(dev_priv->panel_fixed_mode->vdisplay));
}
/* Enable CPU pipe */ /* Enable CPU pipe */
temp = I915_READ(pipeconf_reg); temp = I915_READ(pipeconf_reg);
if ((temp & PIPEACONF_ENABLE) == 0) { if ((temp & PIPEACONF_ENABLE) == 0) {

7
drivers/gpu/drm/i915/intel_lvds.c
View File

@ -296,6 +296,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
goto out; goto out;
} }
/* full screen scale for now */
if (IS_IGDNG(dev))
goto out;
/* 965+ wants fuzzy fitting */ /* 965+ wants fuzzy fitting */
if (IS_I965G(dev)) if (IS_I965G(dev))
pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) | pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
@ -323,8 +327,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
* to register description and PRM. * to register description and PRM.
* Change the value here to see the borders for debugging * Change the value here to see the borders for debugging
*/ */
if (!IS_IGDNG(dev)) {
I915_WRITE(BCLRPAT_A, 0); I915_WRITE(BCLRPAT_A, 0);
I915_WRITE(BCLRPAT_B, 0); I915_WRITE(BCLRPAT_B, 0);
}
switch (lvds_priv->fitting_mode) { switch (lvds_priv->fitting_mode) {
case DRM_MODE_SCALE_CENTER: case DRM_MODE_SCALE_CENTER:
@ -573,7 +579,6 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
* settings. * settings.
*/ */
/* No panel fitting yet, fixme */
if (IS_IGDNG(dev)) if (IS_IGDNG(dev))
return; return;