forked from Minki/linux
clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()
This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -17,11 +17,22 @@
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#include <linux/of_address.h>
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#include "clk.h"
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#include "clk-pll.h"
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#define APLL_LOCK 0x0
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#define APLL_CON0 0x100
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#define SRC_CPU 0x200
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#define DIV_CPU0 0x500
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#define MPLL_LOCK 0x4000
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#define MPLL_CON0 0x4100
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#define SRC_CORE1 0x4204
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#define CPLL_LOCK 0x10020
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#define EPLL_LOCK 0x10030
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#define VPLL_LOCK 0x10040
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#define GPLL_LOCK 0x10050
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#define CPLL_CON0 0x10120
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#define EPLL_CON0 0x10130
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#define VPLL_CON0 0x10140
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#define GPLL_CON0 0x10150
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#define SRC_TOP0 0x10210
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#define SRC_TOP2 0x10218
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#define SRC_GSCL 0x10220
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@ -59,11 +70,19 @@
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#define GATE_IP_FSYS 0x10944
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#define GATE_IP_PERIC 0x10950
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#define GATE_IP_PERIS 0x10960
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#define BPLL_LOCK 0x20010
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#define BPLL_CON0 0x20110
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#define SRC_CDREX 0x20200
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#define PLL_DIV2_SEL 0x20a24
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#define GATE_IP_DISP1 0x10928
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#define GATE_IP_ACP 0x10000
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/* list of PLLs to be registered */
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enum exynos5250_plls {
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apll, mpll, cpll, epll, vpll, gpll, bpll,
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nr_plls /* number of PLLs */
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};
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/*
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* Let each supported clock get a unique id. This id is used to lookup the clock
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* for device tree based platforms. The clocks are categorized into three
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@ -80,7 +99,8 @@ enum exynos5250_clks {
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none,
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/* core clocks */
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fin_pll,
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fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
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fout_epll, fout_vpll,
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/* gate for special clocks (sclk) */
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sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
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@ -471,6 +491,23 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
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GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
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};
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struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = {
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[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0, "fout_apll"),
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[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0, "fout_mpll"),
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[bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
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BPLL_CON0),
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[gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK,
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GPLL_CON0),
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[cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
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CPLL_CON0),
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[epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
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EPLL_CON0),
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[vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc",
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VPLL_LOCK, VPLL_CON0),
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};
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static __initdata struct of_device_id ext_clk_match[] = {
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{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
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{ },
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@ -480,7 +517,6 @@ static __initdata struct of_device_id ext_clk_match[] = {
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static void __init exynos5250_clk_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
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if (np) {
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reg_base = of_iomap(np, 0);
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@ -496,22 +532,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
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samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
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ext_clk_match);
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apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
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reg_base + 0x100);
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mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
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reg_base + 0x4100);
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bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
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reg_base + 0x20110);
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gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
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reg_base + 0x10150);
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cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
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reg_base + 0x10120);
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epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
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reg_base + 0x10130);
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vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
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reg_base + 0x10140);
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samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
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reg_base);
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samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
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ARRAY_SIZE(exynos5250_fixed_rate_clks));
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samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
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