forked from Minki/linux
habanalabs: add support for f/w reset
When the f/w runs in secured mode, it can reset the ASIC when certain events occur. In unsecured mode, the driver asks the f/w to reset the ASIC for those events. We need to perform the entire reset procedure but without accessing the ASIC. i.e. without halting the engines and without sending messages to the f/w. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
parent
56e753d595
commit
8d9aa980be
@ -311,9 +311,15 @@ static void device_hard_reset_pending(struct work_struct *work)
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container_of(work, struct hl_device_reset_work,
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reset_work.work);
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struct hl_device *hdev = device_reset_work->hdev;
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u32 flags;
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int rc;
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rc = hl_device_reset(hdev, HL_RESET_HARD | HL_RESET_FROM_RESET_THREAD);
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flags = HL_RESET_HARD | HL_RESET_FROM_RESET_THREAD;
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if (device_reset_work->fw_reset)
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flags |= HL_RESET_FW;
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rc = hl_device_reset(hdev, flags);
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if ((rc == -EBUSY) && !hdev->device_fini_pending) {
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dev_info(hdev->dev,
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"Could not reset device. will try again in %u seconds",
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@ -702,7 +708,7 @@ static void take_release_locks(struct hl_device *hdev)
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mutex_unlock(&hdev->fpriv_list_lock);
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}
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static void cleanup_resources(struct hl_device *hdev, bool hard_reset)
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static void cleanup_resources(struct hl_device *hdev, bool hard_reset, bool fw_reset)
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{
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if (hard_reset)
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device_late_fini(hdev);
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@ -712,7 +718,7 @@ static void cleanup_resources(struct hl_device *hdev, bool hard_reset)
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* completions from H/W and we won't have any accesses from the
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* H/W to the host machine
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*/
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hdev->asic_funcs->halt_engines(hdev, hard_reset);
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hdev->asic_funcs->halt_engines(hdev, hard_reset, fw_reset);
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/* Go over all the queues, release all CS and their jobs */
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hl_cs_rollback_all(hdev);
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@ -922,7 +928,7 @@ static void device_disable_open_processes(struct hl_device *hdev)
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int hl_device_reset(struct hl_device *hdev, u32 flags)
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{
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u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
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bool hard_reset, from_hard_reset_thread, hard_instead_soft = false;
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bool hard_reset, from_hard_reset_thread, fw_reset, hard_instead_soft = false;
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int i, rc;
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if (!hdev->init_done) {
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@ -933,6 +939,7 @@ int hl_device_reset(struct hl_device *hdev, u32 flags)
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hard_reset = !!(flags & HL_RESET_HARD);
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from_hard_reset_thread = !!(flags & HL_RESET_FROM_RESET_THREAD);
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fw_reset = !!(flags & HL_RESET_FW);
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if (!hard_reset && !hdev->supports_soft_reset) {
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hard_instead_soft = true;
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@ -984,11 +991,13 @@ do_reset:
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else
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hdev->curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
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/*
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* if reset is due to heartbeat, device CPU is no responsive in
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* which case no point sending PCI disable message to it
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/* If reset is due to heartbeat, device CPU is no responsive in
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* which case no point sending PCI disable message to it.
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*
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* If F/W is performing the reset, no need to send it a message to disable
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* PCI access
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*/
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if (hard_reset && !(flags & HL_RESET_HEARTBEAT)) {
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if (hard_reset && !(flags & (HL_RESET_HEARTBEAT | HL_RESET_FW))) {
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/* Disable PCI access from device F/W so he won't send
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* us additional interrupts. We disable MSI/MSI-X at
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* the halt_engines function and we can't have the F/W
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@ -1018,6 +1027,8 @@ again:
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hdev->process_kill_trial_cnt = 0;
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hdev->device_reset_work.fw_reset = fw_reset;
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/*
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* Because the reset function can't run from heartbeat work,
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* we need to call the reset function from a dedicated work.
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@ -1028,7 +1039,7 @@ again:
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return 0;
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}
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cleanup_resources(hdev, hard_reset);
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cleanup_resources(hdev, hard_reset, fw_reset);
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kill_processes:
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if (hard_reset) {
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@ -1062,7 +1073,7 @@ kill_processes:
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}
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/* Reset the H/W. It will be in idle state after this returns */
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hdev->asic_funcs->hw_fini(hdev, hard_reset);
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hdev->asic_funcs->hw_fini(hdev, hard_reset, fw_reset);
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if (hard_reset) {
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hdev->fw_loader.linux_loaded = false;
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@ -1587,7 +1598,7 @@ void hl_device_fini(struct hl_device *hdev)
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hl_hwmon_fini(hdev);
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cleanup_resources(hdev, true);
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cleanup_resources(hdev, true, false);
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/* Kill processes here after CS rollback. This is because the process
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* can't really exit until all its CSs are done, which is what we
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@ -1606,7 +1617,7 @@ void hl_device_fini(struct hl_device *hdev)
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hl_cb_pool_fini(hdev);
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/* Reset the H/W. It will be in idle state after this returns */
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hdev->asic_funcs->hw_fini(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true, false);
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hdev->fw_loader.linux_loaded = false;
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@ -128,12 +128,17 @@ enum hl_mmu_page_table_location {
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*
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* - HL_RESET_DEVICE_RELEASE
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* Set if reset is due to device release
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*
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* - HL_RESET_FW
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* F/W will perform the reset. No need to ask it to reset the device. This is relevant
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* only when running with secured f/w
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*/
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#define HL_RESET_HARD (1 << 0)
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#define HL_RESET_FROM_RESET_THREAD (1 << 1)
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#define HL_RESET_HEARTBEAT (1 << 2)
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#define HL_RESET_TDR (1 << 3)
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#define HL_RESET_DEVICE_RELEASE (1 << 4)
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#define HL_RESET_FW (1 << 5)
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#define HL_MAX_SOBS_PER_MONITOR 8
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@ -1170,8 +1175,8 @@ struct hl_asic_funcs {
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int (*sw_init)(struct hl_device *hdev);
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int (*sw_fini)(struct hl_device *hdev);
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int (*hw_init)(struct hl_device *hdev);
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void (*hw_fini)(struct hl_device *hdev, bool hard_reset);
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void (*halt_engines)(struct hl_device *hdev, bool hard_reset);
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void (*hw_fini)(struct hl_device *hdev, bool hard_reset, bool fw_reset);
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void (*halt_engines)(struct hl_device *hdev, bool hard_reset, bool fw_reset);
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int (*suspend)(struct hl_device *hdev);
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int (*resume)(struct hl_device *hdev);
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int (*mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
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@ -2138,11 +2143,13 @@ struct hwmon_chip_info;
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* @wq: work queue for device reset procedure.
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* @reset_work: reset work to be done.
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* @hdev: habanalabs device structure.
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* @fw_reset: whether f/w will do the reset without us sending them a message to do it.
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*/
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struct hl_device_reset_work {
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struct workqueue_struct *wq;
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struct delayed_work reset_work;
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struct hl_device *hdev;
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bool fw_reset;
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};
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/**
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@ -535,7 +535,7 @@ hl_pci_err_detected(struct pci_dev *pdev, pci_channel_state_t state)
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result = PCI_ERS_RESULT_NONE;
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}
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hdev->asic_funcs->halt_engines(hdev, true);
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hdev->asic_funcs->halt_engines(hdev, true, false);
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return result;
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}
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@ -833,14 +833,14 @@ pci_init:
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GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC);
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if (rc) {
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if (hdev->reset_on_preboot_fail)
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hdev->asic_funcs->hw_fini(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true, false);
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goto pci_fini;
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}
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if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
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dev_info(hdev->dev,
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"H/W state is dirty, must reset before initializing\n");
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hdev->asic_funcs->hw_fini(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true, false);
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}
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return 0;
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@ -3836,7 +3836,7 @@ static void gaudi_disable_timestamp(struct hl_device *hdev)
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WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
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}
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static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset)
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static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
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{
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u32 wait_timeout_ms;
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@ -3848,6 +3848,9 @@ static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset)
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else
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wait_timeout_ms = GAUDI_RESET_WAIT_MSEC;
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if (fw_reset)
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goto skip_engines;
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gaudi_stop_nic_qmans(hdev);
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gaudi_stop_mme_qmans(hdev);
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gaudi_stop_tpc_qmans(hdev);
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@ -3873,6 +3876,7 @@ static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset)
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gaudi_disable_timestamp(hdev);
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skip_engines:
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gaudi_disable_msi(hdev);
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}
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@ -4240,7 +4244,7 @@ disable_queues:
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return rc;
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}
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static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset)
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static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
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{
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struct cpu_dyn_regs *dyn_regs =
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&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
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@ -4261,6 +4265,14 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset)
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cpu_timeout_ms = GAUDI_CPU_RESET_WAIT_MSEC;
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}
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if (fw_reset) {
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dev_info(hdev->dev,
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"Firmware performs HARD reset, going to wait %dms\n",
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reset_timeout_ms);
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goto skip_reset;
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}
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driver_performs_reset = !!(!hdev->asic_prop.fw_security_enabled &&
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!hdev->asic_prop.hard_reset_done_by_fw);
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@ -4337,6 +4349,7 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset)
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reset_timeout_ms);
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}
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skip_reset:
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/*
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* After hard reset, we can't poll the BTM_FSM register because the PSOC
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* itself is in reset. Need to wait until the reset is deasserted
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@ -7999,10 +8012,10 @@ static void gaudi_handle_eqe(struct hl_device *hdev,
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tpc_dec_event_to_tpc_id(event_type),
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"AXI_SLV_DEC_Error");
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if (reset_required) {
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dev_err(hdev->dev, "hard reset required due to %s\n",
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dev_err(hdev->dev, "reset required due to %s\n",
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gaudi_irq_map_table[event_type].name);
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goto reset_device;
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hl_device_reset(hdev, 0);
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} else {
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hl_fw_unmask_irq(hdev, event_type);
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}
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@ -8021,10 +8034,10 @@ static void gaudi_handle_eqe(struct hl_device *hdev,
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tpc_krn_event_to_tpc_id(event_type),
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"KRN_ERR");
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if (reset_required) {
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dev_err(hdev->dev, "hard reset required due to %s\n",
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dev_err(hdev->dev, "reset required due to %s\n",
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gaudi_irq_map_table[event_type].name);
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goto reset_device;
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hl_device_reset(hdev, 0);
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} else {
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hl_fw_unmask_irq(hdev, event_type);
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}
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@ -8154,7 +8167,9 @@ static void gaudi_handle_eqe(struct hl_device *hdev,
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return;
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reset_device:
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if (hdev->hard_reset_on_fw_events)
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if (hdev->asic_prop.fw_security_enabled)
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hl_device_reset(hdev, HL_RESET_HARD | HL_RESET_FW);
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else if (hdev->hard_reset_on_fw_events)
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hl_device_reset(hdev, HL_RESET_HARD);
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else
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hl_fw_unmask_irq(hdev, event_type);
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@ -654,14 +654,14 @@ pci_init:
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GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
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if (rc) {
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if (hdev->reset_on_preboot_fail)
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hdev->asic_funcs->hw_fini(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true, false);
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goto pci_fini;
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}
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if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
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dev_info(hdev->dev,
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"H/W state is dirty, must reset before initializing\n");
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hdev->asic_funcs->hw_fini(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true, false);
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}
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if (!hdev->pldm) {
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@ -2380,7 +2380,7 @@ static void goya_disable_timestamp(struct hl_device *hdev)
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WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
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}
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static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
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static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
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{
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u32 wait_timeout_ms;
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@ -2703,14 +2703,7 @@ disable_queues:
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return rc;
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}
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/*
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* goya_hw_fini - Goya hardware tear-down code
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*
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* @hdev: pointer to hl_device structure
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* @hard_reset: should we do hard reset to all engines or just reset the
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* compute/dma engines
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*/
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static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
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static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
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{
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struct goya_device *goya = hdev->asic_specific;
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u32 reset_timeout_ms, cpu_timeout_ms, status;
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