forked from Minki/linux
Merge branch 'micrel-next'
Johan Hovold says: ==================== net: phy: micrel: refactoring and KSZ8081/KSZ8091 features This series cleans up and refactors parts of the micrel PHY driver, and adds support for broadcast-address-disable and led-mode configuration for KSZ8081 and KSZ8091 PHYs. Specifically, this enables dual KSZ8081 setups (which are limited to using address 0 and 3). A follow up series will add device-type abstraction which will allow for further refactoring and shared initialisation code. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
8d326d818a
@ -14,6 +14,8 @@ Optional properties:
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KSZ8021: register 0x1f, bits 5..4
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KSZ8031: register 0x1f, bits 5..4
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KSZ8051: register 0x1f, bits 5..4
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KSZ8081: register 0x1f, bits 5..4
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KSZ8091: register 0x1f, bits 5..4
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See the respective PHY datasheet for the mode values.
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@ -19,7 +19,6 @@ Optional Properties:
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specifications. If neither of these are specified, the default is to
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assume clause 22. The compatible list may also contain other
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elements.
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- max-speed: Maximum PHY supported speed (10, 100, 1000...)
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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@ -29,6 +28,8 @@ Optional Properties:
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4 hex digits. This is the chip vendor OUI bits 19:24,
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followed by 10 bits of a vendor specific ID.
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- max-speed: Maximum PHY supported speed (10, 100, 1000...)
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Example:
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ethernet-phy@0 {
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@ -30,30 +30,34 @@
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/* Operation Mode Strap Override */
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#define MII_KSZPHY_OMSO 0x16
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#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
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#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
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#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
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#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
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#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
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#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
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/* general Interrupt control/status reg in vendor specific block. */
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#define MII_KSZPHY_INTCS 0x1B
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#define KSZPHY_INTCS_JABBER (1 << 15)
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#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
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#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
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#define KSZPHY_INTCS_PARELLEL (1 << 12)
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#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
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#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
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#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
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#define KSZPHY_INTCS_LINK_UP (1 << 8)
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#define KSZPHY_INTCS_JABBER BIT(15)
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#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
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#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
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#define KSZPHY_INTCS_PARELLEL BIT(12)
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#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
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#define KSZPHY_INTCS_LINK_DOWN BIT(10)
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#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
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#define KSZPHY_INTCS_LINK_UP BIT(8)
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#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
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KSZPHY_INTCS_LINK_DOWN)
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/* general PHY control reg in vendor specific block. */
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#define MII_KSZPHY_CTRL 0x1F
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/* PHY Control 1 */
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#define MII_KSZPHY_CTRL_1 0x1e
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/* PHY Control 2 / PHY Control (if no PHY Control 1) */
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#define MII_KSZPHY_CTRL_2 0x1f
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#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
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/* bitmap of PHY register to set interrupt mode */
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#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
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#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
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#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
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#define KSZ9021_CTRL_INT_ACTIVE_HIGH BIT(14)
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#define KS8737_CTRL_INT_ACTIVE_HIGH BIT(14)
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#define KSZ8051_RMII_50MHZ_CLK BIT(7)
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/* Write/read to/from extended registers */
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#define MII_KSZPHY_EXTREG 0x0b
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@ -122,6 +126,8 @@ static int kszphy_config_intr(struct phy_device *phydev)
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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if (temp < 0)
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return temp;
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temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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@ -134,6 +140,8 @@ static int ksz9021_config_intr(struct phy_device *phydev)
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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if (temp < 0)
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return temp;
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temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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@ -146,19 +154,20 @@ static int ks8737_config_intr(struct phy_device *phydev)
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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if (temp < 0)
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return temp;
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temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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return rc < 0 ? rc : 0;
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}
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static int kszphy_setup_led(struct phy_device *phydev,
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unsigned int reg, unsigned int shift)
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static int kszphy_setup_led(struct phy_device *phydev, u32 reg)
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{
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struct device *dev = &phydev->dev;
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struct device_node *of_node = dev->of_node;
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int rc, temp;
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int rc, temp, shift;
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u32 val;
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if (!of_node && dev->parent->of_node)
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@ -167,15 +176,55 @@ static int kszphy_setup_led(struct phy_device *phydev,
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if (of_property_read_u32(of_node, "micrel,led-mode", &val))
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return 0;
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if (val > 3) {
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dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", val);
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return -EINVAL;
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}
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switch (reg) {
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case MII_KSZPHY_CTRL_1:
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shift = 14;
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break;
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case MII_KSZPHY_CTRL_2:
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shift = 4;
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break;
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default:
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return -EINVAL;
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}
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temp = phy_read(phydev, reg);
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if (temp < 0)
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return temp;
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if (temp < 0) {
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rc = temp;
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goto out;
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}
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temp &= ~(3 << shift);
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temp |= val << shift;
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rc = phy_write(phydev, reg, temp);
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out:
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if (rc < 0)
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dev_err(&phydev->dev, "failed to set led mode\n");
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return rc < 0 ? rc : 0;
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return rc;
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}
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/* Disable PHY address 0 as the broadcast address, so that it can be used as a
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* unique (non-broadcast) address on a shared bus.
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*/
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static int kszphy_broadcast_disable(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_KSZPHY_OMSO);
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if (ret < 0)
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goto out;
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ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
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out:
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if (ret)
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dev_err(&phydev->dev, "failed to disable broadcast address\n");
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return ret;
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}
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static int kszphy_config_init(struct phy_device *phydev)
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@ -185,23 +234,21 @@ static int kszphy_config_init(struct phy_device *phydev)
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static int kszphy_config_init_led8041(struct phy_device *phydev)
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{
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/* single led control, register 0x1e bits 15..14 */
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return kszphy_setup_led(phydev, 0x1e, 14);
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return kszphy_setup_led(phydev, MII_KSZPHY_CTRL_1);
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}
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static int ksz8021_config_init(struct phy_device *phydev)
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{
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const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
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int rc;
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rc = kszphy_setup_led(phydev, 0x1f, 4);
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if (rc)
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dev_err(&phydev->dev, "failed to set led mode\n");
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kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
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rc = ksz_config_flags(phydev);
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if (rc < 0)
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return rc;
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rc = phy_write(phydev, MII_KSZPHY_OMSO, val);
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rc = kszphy_broadcast_disable(phydev);
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return rc < 0 ? rc : 0;
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}
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@ -209,14 +256,20 @@ static int ks8051_config_init(struct phy_device *phydev)
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{
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int rc;
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rc = kszphy_setup_led(phydev, 0x1f, 4);
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if (rc)
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dev_err(&phydev->dev, "failed to set led mode\n");
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kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
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rc = ksz_config_flags(phydev);
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return rc < 0 ? rc : 0;
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}
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static int ksz8081_config_init(struct phy_device *phydev)
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{
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kszphy_broadcast_disable(phydev);
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kszphy_setup_led(phydev, MII_KSZPHY_CTRL_2);
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return 0;
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}
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static int ksz9021_load_values_from_of(struct phy_device *phydev,
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struct device_node *of_node, u16 reg,
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char *field1, char *field2,
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@ -394,8 +447,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
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}
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#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
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#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
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static int ksz8873mll_read_status(struct phy_device *phydev)
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{
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int regval;
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@ -579,7 +632,7 @@ static struct phy_driver ksphy_driver[] = {
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.phy_id_mask = 0x00fffff0,
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init,
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.config_init = ksz8081_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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