forked from Minki/linux
watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family
This patch adds watchdog controller driver for ZTE's zx2967 family. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Baoyou Xie
Guenter Roeck
parent
df823c19e5
commit
8ce6796dab
@ -725,6 +725,16 @@ config ASPEED_WATCHDOG
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To compile this driver as a module, choose M here: the
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module will be called aspeed_wdt.
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config ZX2967_WATCHDOG
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tristate "ZTE zx2967 SoCs watchdog support"
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depends on ARCH_ZX
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select WATCHDOG_CORE
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help
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Say Y here to include support for the watchdog timer
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in ZTE zx2967 SoCs.
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To compile this driver as a module, choose M here: the
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module will be called zx2967_wdt.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -83,6 +83,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
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obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
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obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
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obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
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obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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291
drivers/watchdog/zx2967_wdt.c
Normal file
291
drivers/watchdog/zx2967_wdt.c
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@ -0,0 +1,291 @@
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/*
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* watchdog driver for ZTE's zx2967 family
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*
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* Copyright (C) 2017 ZTE Ltd.
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*
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* Author: Baoyou Xie <baoyou.xie@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/watchdog.h>
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#define ZX2967_WDT_CFG_REG 0x4
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#define ZX2967_WDT_LOAD_REG 0x8
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#define ZX2967_WDT_REFRESH_REG 0x18
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#define ZX2967_WDT_START_REG 0x1c
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#define ZX2967_WDT_REFRESH_MASK GENMASK(5, 0)
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#define ZX2967_WDT_CFG_DIV(n) ((((n) & 0xff) - 1) << 8)
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#define ZX2967_WDT_START_EN 0x1
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/*
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* Hardware magic number.
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* When watchdog reg is written, the lowest 16 bits are valid, but
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* the highest 16 bits should be always this number.
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*/
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#define ZX2967_WDT_WRITEKEY (0x1234 << 16)
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#define ZX2967_WDT_VAL_MASK GENMASK(15, 0)
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#define ZX2967_WDT_DIV_DEFAULT 16
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#define ZX2967_WDT_DEFAULT_TIMEOUT 32
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#define ZX2967_WDT_MIN_TIMEOUT 1
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#define ZX2967_WDT_MAX_TIMEOUT 524
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#define ZX2967_WDT_MAX_COUNT 0xffff
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#define ZX2967_WDT_CLK_FREQ 0x8000
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#define ZX2967_WDT_FLAG_REBOOT_MON BIT(0)
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struct zx2967_wdt {
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struct watchdog_device wdt_device;
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void __iomem *reg_base;
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struct clk *clock;
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};
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static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
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{
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return readl_relaxed(wdt->reg_base + reg);
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}
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static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
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{
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writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
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}
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static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
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{
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u32 val;
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val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG);
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/*
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* Bit 4-5, 1 and 2: refresh config info
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* Bit 2-3, 1 and 2: refresh counter
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* Bit 0-1, 1 and 2: refresh int-value
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* we shift each group value between 1 and 2 to refresh all data.
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*/
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val ^= ZX2967_WDT_REFRESH_MASK;
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zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG,
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val & ZX2967_WDT_VAL_MASK);
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}
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static int
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zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
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{
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struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
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unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
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u32 count;
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count = timeout * ZX2967_WDT_CLK_FREQ;
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if (count > divisor * ZX2967_WDT_MAX_COUNT)
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divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
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count = DIV_ROUND_UP(count, divisor);
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zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG,
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ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK);
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zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG,
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count & ZX2967_WDT_VAL_MASK);
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zx2967_wdt_refresh(wdt);
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wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ;
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return 0;
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}
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static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
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{
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u32 val;
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val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
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val |= ZX2967_WDT_START_EN;
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zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
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val & ZX2967_WDT_VAL_MASK);
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}
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static void __zx2967_wdt_stop(struct zx2967_wdt *wdt)
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{
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u32 val;
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val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
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val &= ~ZX2967_WDT_START_EN;
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zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
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val & ZX2967_WDT_VAL_MASK);
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}
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static int zx2967_wdt_start(struct watchdog_device *wdd)
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{
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struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
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zx2967_wdt_set_timeout(wdd, wdd->timeout);
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__zx2967_wdt_start(wdt);
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return 0;
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}
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static int zx2967_wdt_stop(struct watchdog_device *wdd)
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{
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struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
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__zx2967_wdt_stop(wdt);
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return 0;
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}
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static int zx2967_wdt_keepalive(struct watchdog_device *wdd)
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{
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struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
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zx2967_wdt_refresh(wdt);
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return 0;
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}
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#define ZX2967_WDT_OPTIONS \
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(WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
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static const struct watchdog_info zx2967_wdt_ident = {
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.options = ZX2967_WDT_OPTIONS,
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.identity = "zx2967 watchdog",
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};
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static struct watchdog_ops zx2967_wdt_ops = {
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.owner = THIS_MODULE,
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.start = zx2967_wdt_start,
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.stop = zx2967_wdt_stop,
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.ping = zx2967_wdt_keepalive,
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.set_timeout = zx2967_wdt_set_timeout,
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};
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static void zx2967_wdt_reset_sysctrl(struct device *dev)
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{
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int ret;
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void __iomem *regmap;
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unsigned int offset, mask, config;
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struct of_phandle_args out_args;
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ret = of_parse_phandle_with_fixed_args(dev->of_node,
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"zte,wdt-reset-sysctrl", 3, 0, &out_args);
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if (ret)
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return;
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offset = out_args.args[0];
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config = out_args.args[1];
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mask = out_args.args[2];
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regmap = syscon_node_to_regmap(out_args.np);
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if (IS_ERR(regmap)) {
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of_node_put(out_args.np);
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return;
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}
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regmap_update_bits(regmap, offset, mask, config);
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of_node_put(out_args.np);
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}
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static int zx2967_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct zx2967_wdt *wdt;
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struct resource *base;
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int ret;
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struct reset_control *rstc;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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platform_set_drvdata(pdev, wdt);
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wdt->wdt_device.info = &zx2967_wdt_ident;
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wdt->wdt_device.ops = &zx2967_wdt_ops;
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wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
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wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT;
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wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT;
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wdt->wdt_device.parent = &pdev->dev;
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base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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wdt->reg_base = devm_ioremap_resource(dev, base);
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if (IS_ERR(wdt->reg_base)) {
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dev_err(dev, "ioremap failed\n");
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return PTR_ERR(wdt->reg_base);
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}
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zx2967_wdt_reset_sysctrl(dev);
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wdt->clock = devm_clk_get(dev, NULL);
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if (IS_ERR(wdt->clock)) {
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dev_err(dev, "failed to find watchdog clock source\n");
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return PTR_ERR(wdt->clock);
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}
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ret = clk_prepare_enable(wdt->clock);
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if (ret < 0) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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clk_set_rate(wdt->clock, ZX2967_WDT_CLK_FREQ);
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rstc = devm_reset_control_get(dev, NULL);
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if (IS_ERR(rstc)) {
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dev_err(dev, "failed to get rstc");
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ret = PTR_ERR(rstc);
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goto err;
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}
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reset_control_assert(rstc);
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reset_control_deassert(rstc);
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watchdog_set_drvdata(&wdt->wdt_device, wdt);
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watchdog_init_timeout(&wdt->wdt_device,
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ZX2967_WDT_DEFAULT_TIMEOUT, dev);
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watchdog_set_nowayout(&wdt->wdt_device, WATCHDOG_NOWAYOUT);
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ret = watchdog_register_device(&wdt->wdt_device);
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if (ret)
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goto err;
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dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)",
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wdt->wdt_device.timeout, WATCHDOG_NOWAYOUT);
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return 0;
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err:
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clk_disable_unprepare(wdt->clock);
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return ret;
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}
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static int zx2967_wdt_remove(struct platform_device *pdev)
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{
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struct zx2967_wdt *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdt_device);
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clk_disable_unprepare(wdt->clock);
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return 0;
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}
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static const struct of_device_id zx2967_wdt_match[] = {
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{ .compatible = "zte,zx296718-wdt", },
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{}
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};
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MODULE_DEVICE_TABLE(of, zx2967_wdt_match);
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static struct platform_driver zx2967_wdt_driver = {
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.probe = zx2967_wdt_probe,
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.remove = zx2967_wdt_remove,
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.driver = {
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.name = "zx2967-wdt",
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.of_match_table = of_match_ptr(zx2967_wdt_match),
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},
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};
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module_platform_driver(zx2967_wdt_driver);
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MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
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MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver");
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MODULE_LICENSE("GPL v2");
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