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drm/amd/display: Program DSC during timing programming

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[why]
Link or DIG BE can't be exposed to a higher stream bandwidth than they
can handle. When DSC is required to fit the stream into the link
bandwidth, DSC has to be programmed during timing programming to ensure
this. Without it, intermittent issues such as black screen after S3 or a
hot-plug can be seen.

[how]
Move DSC programming from enabling stream on link to timing setup.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nikola Cornij 2020-02-26 14:53:54 -05:00 committed by Alex Deucher
parent 4c631826e0
commit 8cc426d79b
4 changed files with 17 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -3078,9 +3078,14 @@ void core_link_enable_stream(
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
dc_is_virtual_signal(pipe_ctx->stream->signal))
dp_set_dsc_enable(pipe_ctx, true);
dc_is_virtual_signal(pipe_ctx->stream->signal)) {
/* Here we only need to enable DSC on RX. DSC HW programming
* was done earlier, as part of timing programming.
*/
dp_set_dsc_on_rx(pipe_ctx, true);
}
}
dc->hwss.enable_stream(pipe_ctx);
/* Set DPS PPS SDP (AKA "info frames") */
@ -3107,7 +3112,7 @@ void core_link_enable_stream(
} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
dc_is_virtual_signal(pipe_ctx->stream->signal))
dp_set_dsc_enable(pipe_ctx, true);
dp_set_dsc_on_rx(pipe_ctx, true);
}
}

2
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View File

@ -394,7 +394,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
DC_LOG_DSC("\tslice_width %d", config->slice_width);
}
static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
{
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;

7
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -623,6 +623,13 @@ enum dc_status dcn20_enable_stream_timing(
/* TODO check if timing_changed, disable stream if timing changed */
/* Have to setup DSC here to make sure the bandwidth sent to DIG BE won't be bigger than
* what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag will be automatically
* set at a later time when the video is enabled (DP_VID_STREAM_EN = 1).
*/
if (pipe_ctx->stream->timing.flags.DSC)
dp_set_dsc_on_stream(pipe_ctx, true);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
opp_cnt++;

1
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
View File

@ -85,6 +85,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable);
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
#endif /* __DC_LINK_DP_H__ */