forked from Minki/linux
Merge series "spi: stm32: various driver fixes" from Alain Volmat <alain.volmat@st.com>:
This serie is a reduced version of the serie [spi: stm32: various driver enhancements] previously sent. Alain Volmat (1): spi: stm32: always perform registers configuration prior to transfer Amelie Delaunay (3): spi: stm32: fix fifo threshold level in case of short transfer spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate spi: stm32: fixes suspend/resume management Antonio Borneo (1): spi: stm32h7: fix race condition at end of transfer drivers/spi/spi-stm32.c | 98 ++++++++++++++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 37 deletions(-) -- v2: fix conditional statement within [spi: stm32: fix fifo threshold level in case of short transfer] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
This commit is contained in:
Mark Brown
commit
8cb61d65b1
@ -13,6 +13,7 @@
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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@ -441,7 +442,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
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{
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u32 div, mbrdiv;
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div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
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/* Ensure spi->clk_rate is even */
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div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
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/*
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* SPI framework set xfer->speed_hz to master->max_speed_hz if
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@ -467,20 +469,27 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
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/**
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* stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
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* @spi: pointer to the spi controller data structure
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* @xfer_len: length of the message to be transferred
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*/
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static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
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static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
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{
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u32 fthlv, half_fifo;
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u32 fthlv, half_fifo, packet;
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/* data packet should not exceed 1/2 of fifo space */
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half_fifo = (spi->fifo_size / 2);
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if (spi->cur_bpw <= 8)
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fthlv = half_fifo;
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else if (spi->cur_bpw <= 16)
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fthlv = half_fifo / 2;
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/* data_packet should not exceed transfer length */
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if (half_fifo > xfer_len)
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packet = xfer_len;
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else
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fthlv = half_fifo / 4;
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packet = half_fifo;
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if (spi->cur_bpw <= 8)
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fthlv = packet;
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else if (spi->cur_bpw <= 16)
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fthlv = packet / 2;
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else
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fthlv = packet / 4;
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/* align packet size with data registers access */
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if (spi->cur_bpw > 8)
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@ -488,6 +497,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
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else
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fthlv -= (fthlv % 4); /* multiple of 4 */
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if (!fthlv)
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fthlv = 1;
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return fthlv;
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}
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@ -971,8 +983,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
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spin_unlock_irqrestore(&spi->lock, flags);
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if (end) {
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spi_finalize_current_transfer(master);
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stm32h7_spi_disable(spi);
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spi_finalize_current_transfer(master);
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}
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return IRQ_HANDLED;
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@ -1393,7 +1405,7 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
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cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
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STM32H7_SPI_CFG1_DSIZE;
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spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
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spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
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fthlv = spi->cur_fthlv - 1;
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cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
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@ -1585,39 +1597,33 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
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unsigned long flags;
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unsigned int comm_type;
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int nb_words, ret = 0;
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int mbr;
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spin_lock_irqsave(&spi->lock, flags);
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if (spi->cur_bpw != transfer->bits_per_word) {
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spi->cur_bpw = transfer->bits_per_word;
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spi->cfg->set_bpw(spi);
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spi->cur_xferlen = transfer->len;
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spi->cur_bpw = transfer->bits_per_word;
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spi->cfg->set_bpw(spi);
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/* Update spi->cur_speed with real clock speed */
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mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
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spi->cfg->baud_rate_div_min,
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spi->cfg->baud_rate_div_max);
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if (mbr < 0) {
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ret = mbr;
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goto out;
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}
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if (spi->cur_speed != transfer->speed_hz) {
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int mbr;
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/* Update spi->cur_speed with real clock speed */
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mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
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spi->cfg->baud_rate_div_min,
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spi->cfg->baud_rate_div_max);
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if (mbr < 0) {
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ret = mbr;
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goto out;
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}
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transfer->speed_hz = spi->cur_speed;
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stm32_spi_set_mbr(spi, mbr);
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}
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transfer->speed_hz = spi->cur_speed;
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stm32_spi_set_mbr(spi, mbr);
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comm_type = stm32_spi_communication_type(spi_dev, transfer);
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if (spi->cur_comm != comm_type) {
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ret = spi->cfg->set_mode(spi, comm_type);
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ret = spi->cfg->set_mode(spi, comm_type);
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if (ret < 0)
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goto out;
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if (ret < 0)
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goto out;
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spi->cur_comm = comm_type;
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}
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spi->cur_comm = comm_type;
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if (spi->cfg->set_data_idleness)
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spi->cfg->set_data_idleness(spi, transfer->len);
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@ -1635,8 +1641,6 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
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goto out;
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}
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spi->cur_xferlen = transfer->len;
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dev_dbg(spi->dev, "transfer communication mode set to %d\n",
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spi->cur_comm);
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dev_dbg(spi->dev,
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@ -1996,6 +2000,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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pinctrl_pm_select_sleep_state(&pdev->dev);
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return 0;
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}
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@ -2007,13 +2013,18 @@ static int stm32_spi_runtime_suspend(struct device *dev)
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clk_disable_unprepare(spi->clk);
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return 0;
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return pinctrl_pm_select_sleep_state(dev);
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}
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static int stm32_spi_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct stm32_spi *spi = spi_master_get_devdata(master);
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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return clk_prepare_enable(spi->clk);
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}
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@ -2043,10 +2054,23 @@ static int stm32_spi_resume(struct device *dev)
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return ret;
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ret = spi_master_resume(master);
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if (ret)
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if (ret) {
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clk_disable_unprepare(spi->clk);
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return ret;
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}
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return ret;
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ret = pm_runtime_get_sync(dev);
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if (ret) {
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dev_err(dev, "Unable to power device:%d\n", ret);
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return ret;
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}
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spi->cfg->config(spi);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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}
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#endif
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