Merge branch 'for-5.20/dt-bindings' into for-5.20/memory
This commit is contained in:
Thierry Reding
commit
8c2261e9f0
Documentation/devicetree/bindings/arm/tegra
include/dt-bindings
@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra194 AXI2APB bridge
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^axi2apb@([0-9a-f]+)$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-axi2apb
|
||||
|
||||
reg:
|
||||
maxItems: 6
|
||||
description: Physical base address and length of registers for all bridges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
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axi2apb: axi2apb@2390000 {
|
||||
compatible = "nvidia,tegra194-axi2apb";
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reg = <0x02390000 0x1000>,
|
||||
<0x023a0000 0x1000>,
|
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<0x023b0000 0x1000>,
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<0x023c0000 0x1000>,
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<0x023d0000 0x1000>,
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||||
<0x023e0000 0x1000>;
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||||
};
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||||
@ -0,0 +1,97 @@
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||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
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||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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||||
|
||||
title: NVIDIA Tegra194 CBB 1.0 bindings
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||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
||||
description: |+
|
||||
The Control Backbone (CBB) is comprised of the physical path from an
|
||||
initiator to a target's register configuration space. CBB 1.0 has
|
||||
multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
|
||||
initiators and targets using different bridges like AXIP2P, AXI2APB.
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||||
|
||||
This driver handles errors due to illegal register accesses reported
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||||
by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
|
||||
"AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
|
||||
which is the main NOC.
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||||
|
||||
By default, the access issuing initiator is informed about the error
|
||||
using SError or Data Abort exception unless the ERD (Error Response
|
||||
Disable) is enabled/set for that initiator. If the ERD is enabled, then
|
||||
SError or Data Abort is masked and the error is reported with interrupt.
|
||||
|
||||
- For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
|
||||
errors due to illegal accesses from CCPLEX are reported by interrupts.
|
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If ERD is not set, then error is reported by SError.
|
||||
- For other initiators, the ERD is disabled. So, the access issuing
|
||||
initiator is informed about the illegal access by Data Abort exception.
|
||||
In addition, an interrupt is also generated to CCPLEX. These initiators
|
||||
include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
|
||||
engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
|
||||
engine) etc which can initiate transactions.
|
||||
|
||||
The driver prints relevant debug information like Error Code, Error
|
||||
Description, Master, Address, AXI ID, Cache, Protection, Security Group
|
||||
etc on receiving error notification.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^[a-z]+-noc@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-cbb-noc
|
||||
- nvidia,tegra194-aon-noc
|
||||
- nvidia,tegra194-bpmp-noc
|
||||
- nvidia,tegra194-rce-noc
|
||||
- nvidia,tegra194-sce-noc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
CCPLEX receives secure or nonsecure interrupt depending on error type.
|
||||
A secure interrupt is received for SEC(firewall) & SLV errors and a
|
||||
non-secure interrupt is received for TMO & DEC errors.
|
||||
items:
|
||||
- description: non-secure interrupt
|
||||
- description: secure interrupt
|
||||
|
||||
nvidia,axi2apb:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description:
|
||||
Specifies the node having all axi2apb bridges which need to be checked
|
||||
for any error logged in their status register.
|
||||
|
||||
nvidia,apbmisc:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description:
|
||||
Specifies the apbmisc node which need to be used for reading the ERD
|
||||
register.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- nvidia,apbmisc
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cbb-noc@2300000 {
|
||||
compatible = "nvidia,tegra194-cbb-noc";
|
||||
reg = <0x02300000 0x1000>;
|
||||
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
||||
nvidia,axi2apb = <&axi2apb>;
|
||||
nvidia,apbmisc = <&apbmisc>;
|
||||
};
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra CBB 2.0 bindings
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
||||
description: |+
|
||||
The Control Backbone (CBB) is comprised of the physical path from an
|
||||
initiator to a target's register configuration space. CBB 2.0 consists
|
||||
of multiple sub-blocks connected to each other to create a topology.
|
||||
The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
|
||||
which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
|
||||
"CBB central fabric".
|
||||
|
||||
In CBB 2.0, each initiator which can issue transactions connects to a
|
||||
Root Master Node (MN) before it connects to any other element of the
|
||||
fabric. Each Root MN contains a Error Monitor (EM) which detects and
|
||||
logs error. Interrupts from various EM blocks are collated by Error
|
||||
Notifier (EN) which is per fabric and presents a single interrupt from
|
||||
fabric to the SoC interrupt controller.
|
||||
|
||||
The driver handles errors from CBB due to illegal register accesses
|
||||
and prints debug information about failed transaction on receiving
|
||||
the interrupt from EN. Debug information includes Error Code, Error
|
||||
Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
|
||||
Security Group etc on receiving error notification.
|
||||
|
||||
If the Error Response Disable (ERD) is set/enabled for an initiator,
|
||||
then SError or Data abort exception error response is masked and an
|
||||
interrupt is used for reporting errors due to illegal accesses from
|
||||
that initiator. The value returned on read failures is '0xFFFFFFFF'
|
||||
for compatibility with PCIE.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^[a-z]+-fabric@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra234-aon-fabric
|
||||
- nvidia,tegra234-bpmp-fabric
|
||||
- nvidia,tegra234-cbb-fabric
|
||||
- nvidia,tegra234-dce-fabric
|
||||
- nvidia,tegra234-rce-fabric
|
||||
- nvidia,tegra234-sce-fabric
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: secure interrupt from error notifier
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cbb-fabric@1300000 {
|
||||
compatible = "nvidia,tegra234-cbb-fabric";
|
||||
reg = <0x13a00000 0x400000>;
|
||||
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@ -164,10 +164,111 @@
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||||
#define TEGRA234_CLK_PEX1_C5_CORE 225U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief RX clock recovered from MGBE0 lane input */
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||||
#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
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||||
/** @brief RX clock recovered from MGBE1 lane input */
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#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
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||||
/** @brief RX clock recovered from MGBE2 lane input */
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||||
#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
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||||
/** @brief RX clock recovered from MGBE3 lane input */
|
||||
#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
|
||||
/** @brief 32K input clock provided by PMIC */
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||||
#define TEGRA234_CLK_CLK_32K 289U
|
||||
/** @brief Monitored branch of MBGE0 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
|
||||
/** @brief Monitored branch of MBGE1 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
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||||
/** @brief Monitored branch of MBGE2 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
|
||||
/** @brief Monitored branch of MBGE3 RX input clock */
|
||||
#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
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||||
/** @brief Monitored branch of MGBE0 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
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||||
/** @brief Monitored branch of MGBE1 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
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||||
/** @brief Monitored branch of MGBE2 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
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||||
/** @brief Monitored branch of MGBE3 RX PCS mux output */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
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||||
/** @brief RX PCS clock recovered from MGBE0 lane input */
|
||||
#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
|
||||
/** @brief RX PCS clock recovered from MGBE1 lane input */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
|
||||
/** @brief RX PCS clock recovered from MGBE2 lane input */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
|
||||
/** @brief RX PCS clock recovered from MGBE3 lane input */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
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||||
#define TEGRA234_CLK_MGBE0_RX_PCS 373U
|
||||
/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_TX 374U
|
||||
/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_TX_PCS 375U
|
||||
/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
|
||||
/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_MAC 377U
|
||||
/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_MACSEC 378U
|
||||
/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
|
||||
/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE0_APP 380U
|
||||
/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE0_PTP_REF 381U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE1_RX_PCS 382U
|
||||
/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_TX 383U
|
||||
/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_TX_PCS 384U
|
||||
/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
|
||||
/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_MAC 386U
|
||||
/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
|
||||
/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE1_APP 389U
|
||||
/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE1_PTP_REF 390U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE2_RX_PCS 391U
|
||||
/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_TX 392U
|
||||
/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_TX_PCS 393U
|
||||
/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
|
||||
/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_MAC 395U
|
||||
/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
|
||||
/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE2_APP 398U
|
||||
/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE2_PTP_REF 399U
|
||||
/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
|
||||
#define TEGRA234_CLK_MGBE3_RX_PCS 400U
|
||||
/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_TX 401U
|
||||
/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_TX_PCS 402U
|
||||
/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
|
||||
#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
|
||||
/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_MAC 404U
|
||||
/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_MACSEC 405U
|
||||
/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
|
||||
/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
|
||||
#define TEGRA234_CLK_MGBE3_APP 407U
|
||||
/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
|
||||
#define TEGRA234_CLK_MGBE3_PTP_REF 408U
|
||||
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
|
||||
#define TEGRA234_CLK_AZA_2XBIT 457U
|
||||
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
|
||||
#define TEGRA234_CLK_AZA_BIT 458U
|
||||
|
||||
#endif
|
||||
|
||||
@ -11,11 +11,16 @@
|
||||
/* NISO0 stream IDs */
|
||||
#define TEGRA234_SID_APE 0x02
|
||||
#define TEGRA234_SID_HDA 0x03
|
||||
#define TEGRA234_SID_GPCDMA 0x04
|
||||
#define TEGRA234_SID_MGBE 0x06
|
||||
#define TEGRA234_SID_PCIE0 0x12
|
||||
#define TEGRA234_SID_PCIE4 0x13
|
||||
#define TEGRA234_SID_PCIE5 0x14
|
||||
#define TEGRA234_SID_PCIE6 0x15
|
||||
#define TEGRA234_SID_PCIE9 0x1f
|
||||
#define TEGRA234_SID_MGBE_VF1 0x49
|
||||
#define TEGRA234_SID_MGBE_VF2 0x4a
|
||||
#define TEGRA234_SID_MGBE_VF3 0x4b
|
||||
|
||||
/* NISO1 stream IDs */
|
||||
#define TEGRA234_SID_SDMMC4 0x02
|
||||
@ -61,8 +66,24 @@
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
|
||||
/* PCIE7r1 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
|
||||
/* MGBE0 read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
|
||||
/* MGBEB read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
|
||||
/* MGBEC read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
|
||||
/* MGBED read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
|
||||
/* MGBE0 write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
|
||||
/* MGBEB write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
|
||||
/* MGBEC write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* MGBED write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
/* BPMP read client */
|
||||
|
||||
@ -18,5 +18,6 @@
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEA 17U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBED 20U
|
||||
|
||||
#endif
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#define TEGRA234_RESET_PEX1_COMMON_APB 13U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7 14U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
|
||||
#define TEGRA234_RESET_GPCDMA 18U
|
||||
#define TEGRA234_RESET_HDA 20U
|
||||
#define TEGRA234_RESET_HDACODEC 21U
|
||||
#define TEGRA234_RESET_I2C1 24U
|
||||
@ -29,6 +30,12 @@
|
||||
#define TEGRA234_RESET_I2C7 33U
|
||||
#define TEGRA234_RESET_I2C8 34U
|
||||
#define TEGRA234_RESET_I2C9 35U
|
||||
#define TEGRA234_RESET_MGBE0_PCS 45U
|
||||
#define TEGRA234_RESET_MGBE0_MAC 46U
|
||||
#define TEGRA234_RESET_MGBE1_PCS 49U
|
||||
#define TEGRA234_RESET_MGBE1_MAC 50U
|
||||
#define TEGRA234_RESET_MGBE2_PCS 53U
|
||||
#define TEGRA234_RESET_MGBE2_MAC 54U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10 56U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
|
||||
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
|
||||
@ -43,6 +50,8 @@
|
||||
#define TEGRA234_RESET_QSPI0 76U
|
||||
#define TEGRA234_RESET_QSPI1 77U
|
||||
#define TEGRA234_RESET_SDMMC4 85U
|
||||
#define TEGRA234_RESET_MGBE3_PCS 87U
|
||||
#define TEGRA234_RESET_MGBE3_MAC 88U
|
||||
#define TEGRA234_RESET_UARTA 100U
|
||||
#define TEGRA234_RESET_PEX0_CORE_0 116U
|
||||
#define TEGRA234_RESET_PEX0_CORE_1 117U
|
||||
|
||||
Loading…
Reference in New Issue
Block a user