forked from Minki/linux
iommu/arm-smmu-v3: Add a master->domain pointer
As we're going to track domain-master links more closely for ATS and CD invalidation, add pointer to the attached domain in struct arm_smmu_master. As a result, arm_smmu_strtab_ent is redundant and can be removed. Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Jean-Philippe Brucker
Will Deacon
parent
bcecaee434
commit
8be39a1a04
@ -505,19 +505,6 @@ struct arm_smmu_s2_cfg {
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u64 vtcr;
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};
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struct arm_smmu_strtab_ent {
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/*
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* An STE is "assigned" if the master emitting the corresponding SID
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* is attached to a domain. The behaviour of an unassigned STE is
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* determined by the disable_bypass parameter, whereas an assigned
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* STE behaves according to s1_cfg/s2_cfg, which themselves are
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* configured according to the domain type.
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*/
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bool assigned;
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struct arm_smmu_s1_cfg *s1_cfg;
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struct arm_smmu_s2_cfg *s2_cfg;
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};
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struct arm_smmu_strtab_cfg {
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__le64 *strtab;
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dma_addr_t strtab_dma;
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@ -593,7 +580,7 @@ struct arm_smmu_device {
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/* SMMU private data for each master */
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struct arm_smmu_master {
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struct arm_smmu_device *smmu;
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struct arm_smmu_strtab_ent ste;
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struct arm_smmu_domain *domain;
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u32 *sids;
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unsigned int num_sids;
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};
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@ -1087,8 +1074,8 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
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arm_smmu_cmdq_issue_sync(smmu);
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}
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static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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__le64 *dst, struct arm_smmu_strtab_ent *ste)
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static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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__le64 *dst)
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{
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/*
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* This is hideously complicated, but we only really care about
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@ -1108,6 +1095,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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*/
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u64 val = le64_to_cpu(dst[0]);
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bool ste_live = false;
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struct arm_smmu_device *smmu = NULL;
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struct arm_smmu_s1_cfg *s1_cfg = NULL;
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struct arm_smmu_s2_cfg *s2_cfg = NULL;
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struct arm_smmu_domain *smmu_domain = NULL;
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struct arm_smmu_cmdq_ent prefetch_cmd = {
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.opcode = CMDQ_OP_PREFETCH_CFG,
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.prefetch = {
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@ -1115,6 +1106,25 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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},
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};
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if (master) {
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smmu_domain = master->domain;
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smmu = master->smmu;
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}
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if (smmu_domain) {
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switch (smmu_domain->stage) {
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case ARM_SMMU_DOMAIN_S1:
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s1_cfg = &smmu_domain->s1_cfg;
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break;
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case ARM_SMMU_DOMAIN_S2:
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case ARM_SMMU_DOMAIN_NESTED:
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s2_cfg = &smmu_domain->s2_cfg;
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break;
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default:
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break;
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}
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}
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if (val & STRTAB_STE_0_V) {
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switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {
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case STRTAB_STE_0_CFG_BYPASS:
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@ -1135,8 +1145,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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val = STRTAB_STE_0_V;
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/* Bypass/fault */
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if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) {
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if (!ste->assigned && disable_bypass)
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if (!smmu_domain || !(s1_cfg || s2_cfg)) {
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if (!smmu_domain && disable_bypass)
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
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else
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
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@ -1154,7 +1164,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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return;
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}
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if (ste->s1_cfg) {
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if (s1_cfg) {
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BUG_ON(ste_live);
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dst[1] = cpu_to_le64(
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FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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@ -1169,22 +1179,22 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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!(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
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dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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val |= (s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS);
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}
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if (ste->s2_cfg) {
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if (s2_cfg) {
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BUG_ON(ste_live);
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dst[2] = cpu_to_le64(
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FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) |
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FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) |
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FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) |
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FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) |
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#ifdef __BIG_ENDIAN
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STRTAB_STE_2_S2ENDI |
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#endif
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STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
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STRTAB_STE_2_S2R);
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dst[3] = cpu_to_le64(ste->s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
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dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
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}
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@ -1201,10 +1211,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
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{
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unsigned int i;
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struct arm_smmu_strtab_ent ste = { .assigned = false };
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for (i = 0; i < nent; ++i) {
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arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste);
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arm_smmu_write_strtab_ent(NULL, -1, strtab);
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strtab += STRTAB_STE_DWORDS;
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}
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}
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@ -1706,13 +1715,16 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
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if (j < i)
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continue;
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arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
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arm_smmu_write_strtab_ent(master, sid, step);
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}
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}
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static void arm_smmu_detach_dev(struct arm_smmu_master *master)
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{
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master->ste.assigned = false;
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if (!master->domain)
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return;
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master->domain = NULL;
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arm_smmu_install_ste_for_dev(master);
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}
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@ -1723,18 +1735,14 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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struct arm_smmu_device *smmu;
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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struct arm_smmu_master *master;
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struct arm_smmu_strtab_ent *ste;
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if (!fwspec)
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return -ENOENT;
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master = fwspec->iommu_priv;
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smmu = master->smmu;
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ste = &master->ste;
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/* Already attached to a different domain? */
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if (ste->assigned)
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arm_smmu_detach_dev(master);
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arm_smmu_detach_dev(master);
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mutex_lock(&smmu_domain->init_mutex);
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@ -1754,19 +1762,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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goto out_unlock;
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}
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ste->assigned = true;
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master->domain = smmu_domain;
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS) {
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ste->s1_cfg = NULL;
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ste->s2_cfg = NULL;
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} else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
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ste->s1_cfg = &smmu_domain->s1_cfg;
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ste->s2_cfg = NULL;
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arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
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} else {
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ste->s1_cfg = NULL;
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ste->s2_cfg = &smmu_domain->s2_cfg;
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}
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)
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arm_smmu_write_ctx_desc(smmu, &smmu_domain->s1_cfg);
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arm_smmu_install_ste_for_dev(master);
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out_unlock:
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@ -1921,8 +1920,7 @@ static void arm_smmu_remove_device(struct device *dev)
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master = fwspec->iommu_priv;
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smmu = master->smmu;
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if (master && master->ste.assigned)
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arm_smmu_detach_dev(master);
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arm_smmu_detach_dev(master);
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iommu_group_remove_device(dev);
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iommu_device_unlink(&smmu->iommu, dev);
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kfree(master);
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