forked from Minki/linux
drm/i915: hw state readout for i9xx dplls
In addition to existing stuff we also need to track DPLL_MD on gen4 and vlv. This is prep work so that we can move the dpll enable sequence out from the ->mode_set callback into the crtc enabling functions. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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952735ee41
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8bcc2795a6
@ -144,6 +144,7 @@ enum intel_dpll_id {
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struct intel_dpll_hw_state {
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struct intel_dpll_hw_state {
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uint32_t dpll;
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uint32_t dpll;
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uint32_t dpll_md;
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uint32_t fp0;
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uint32_t fp0;
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uint32_t fp1;
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uint32_t fp1;
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};
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};
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@ -4272,14 +4272,17 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
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}
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}
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I915_WRITE(FP0(pipe), fp);
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I915_WRITE(FP0(pipe), fp);
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crtc->config.dpll_hw_state.fp0 = fp;
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crtc->lowfreq_avail = false;
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crtc->lowfreq_avail = false;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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reduced_clock && i915_powersave) {
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reduced_clock && i915_powersave) {
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I915_WRITE(FP1(pipe), fp2);
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I915_WRITE(FP1(pipe), fp2);
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crtc->config.dpll_hw_state.fp1 = fp2;
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crtc->lowfreq_avail = true;
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crtc->lowfreq_avail = true;
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} else {
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} else {
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I915_WRITE(FP1(pipe), fp);
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I915_WRITE(FP1(pipe), fp);
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crtc->config.dpll_hw_state.fp1 = fp;
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}
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}
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}
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}
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@ -4457,6 +4460,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
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dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
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dpll |= DPLL_VCO_ENABLE;
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dpll |= DPLL_VCO_ENABLE;
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crtc->config.dpll_hw_state.dpll = dpll;
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I915_WRITE(DPLL(pipe), dpll);
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I915_WRITE(DPLL(pipe), dpll);
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POSTING_READ(DPLL(pipe));
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POSTING_READ(DPLL(pipe));
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udelay(150);
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udelay(150);
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@ -4466,6 +4471,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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dpll_md = (crtc->config.pixel_multiplier - 1)
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dpll_md = (crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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crtc->config.dpll_hw_state.dpll_md = dpll_md;
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I915_WRITE(DPLL_MD(pipe), dpll_md);
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I915_WRITE(DPLL_MD(pipe), dpll_md);
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POSTING_READ(DPLL_MD(pipe));
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POSTING_READ(DPLL_MD(pipe));
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@ -4544,6 +4551,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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dpll |= DPLL_VCO_ENABLE;
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crtc->config.dpll_hw_state.dpll = dpll;
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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POSTING_READ(DPLL(pipe));
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udelay(150);
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udelay(150);
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@ -4564,6 +4573,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4) {
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if (INTEL_INFO(dev)->gen >= 4) {
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u32 dpll_md = (crtc->config.pixel_multiplier - 1)
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u32 dpll_md = (crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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crtc->config.dpll_hw_state.dpll_md = dpll_md;
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I915_WRITE(DPLL_MD(pipe), dpll_md);
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I915_WRITE(DPLL_MD(pipe), dpll_md);
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} else {
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} else {
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/* The pixel multiplier can only be updated once the
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/* The pixel multiplier can only be updated once the
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@ -4608,6 +4619,8 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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dpll |= DPLL_VCO_ENABLE;
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crtc->config.dpll_hw_state.dpll = dpll;
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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POSTING_READ(DPLL(pipe));
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udelay(150);
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udelay(150);
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@ -4964,6 +4977,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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pipe_config->pixel_multiplier =
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pipe_config->pixel_multiplier =
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((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
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((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
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>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
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>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
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pipe_config->dpll_hw_state.dpll_md = tmp;
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} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
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} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
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tmp = I915_READ(DPLL(crtc->pipe));
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tmp = I915_READ(DPLL(crtc->pipe));
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pipe_config->pixel_multiplier =
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pipe_config->pixel_multiplier =
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@ -4975,6 +4989,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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* function. */
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* function. */
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pipe_config->pixel_multiplier = 1;
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pipe_config->pixel_multiplier = 1;
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}
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}
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pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
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if (!IS_VALLEYVIEW(dev)) {
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pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
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pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
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}
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return true;
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return true;
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}
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}
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@ -8126,6 +8145,7 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I(shared_dpll);
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PIPE_CONF_CHECK_I(shared_dpll);
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PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
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PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
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PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
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PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
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