forked from Minki/linux
ARM: dts: Amlogic updates for v5.4
Highlights - odroid-c1: use MAC address from efuse - add VDD_EE regulator to several boards -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl1cbb0ACgkQWTcYmtP7 xmXlwhAAhPL9N9p4sLYjGy7CMGYzN9N5SJ7mufADC2K1uTDe7BREtgkFZaFRcnTp MBuCkrLb+aRn8iIsdKHo1Y1uOJ5XHo5kXMCEWzT2BsA9ilzBZ7u+/Zeb3izi7OCy Vti92xWePzsTQqtYBVnOhmwX/QpGLeED3XC+t87IrjI7PMiyGUjq34PPf9QycdAh Ck0o8SFCb8OuVqXsbiCyKkbZs7naAiuJKXIMxRQj/4THE1mMjfgVxKYZpMiUI0pQ CdCucZ5RJ3ylhmA6T8ikhxbUWRrZwrtklgUsPuZAVIyXh/eOYlpCunPsdsDlRm8z a8DfNOzIXLyQWfYrNjFE7NShEPkb7aV4HN4E73CCgvAivthoh5hpcmv4FnFsqH20 frta6qcvKzNpk88mc95NQJ3a5OWVaGK6CJYfGK2VBI6+y5+QKXntUzp9kxiZqysH 6/ghU7xP8QSdynno88UqHubwpyMEfWVAIymS3ziRheu7LX02OIGE0ZEpmzu5e7gU kozGilY6pQr7lHP9K1LlKI1DYi5P3UFGNF09YjZPsp9xiPeQKXAmBkWUrYFdk1+x urpsrL3Pd+RD77ZOq8xTHnO3zL3vKzhIh2ginnzaC9zxjKR72VEgU90SLy/oDboT W8x2oG5UrkDVPMrBSiNWg5IUNqYjSLJonIf+afXbr9cqlwX3Y4I= =zCaj -----END PGP SIGNATURE----- Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.4 Highlights - odroid-c1: use MAC address from efuse - add VDD_EE regulator to several boards * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: odroidc1: use the MAC address stored in the eFuse ARM: dts: meson8b: mxq: add the VDDEE regulator ARM: dts: meson8b: odroidc1: add the VDDEE regulator ARM: dts: meson8b: ec100: add the VDDEE regulator ARM: dts: meson8b: add the PWM_D output pin ARM: dts: meson8b: add ethernet fifo sizes Link: https://lore.kernel.org/r/7hzhk3bi96.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
8ad83e3c8f
@ -219,6 +219,27 @@
|
||||
*/
|
||||
vin-supply = <&vcc_3v3>;
|
||||
};
|
||||
|
||||
vddee: regulator-vddee {
|
||||
/*
|
||||
* Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
|
||||
* Synchronous Step Down Regulator. Also called VDDAO
|
||||
* in a part of the schematics.
|
||||
*/
|
||||
compatible = "pwm-regulator";
|
||||
|
||||
regulator-name = "VDDEE";
|
||||
regulator-min-microvolt = <860000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
pwms = <&pwm_cd 1 1148 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@ -269,6 +290,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mali {
|
||||
mali-supply = <&vddee>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vcc_1v8>;
|
||||
@ -350,10 +375,10 @@
|
||||
|
||||
&pwm_cd {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_c1_pins>;
|
||||
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0";
|
||||
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
|
@ -76,6 +76,22 @@
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddee: regulator-vddee {
|
||||
compatible = "pwm-regulator";
|
||||
|
||||
regulator-name = "VDDEE";
|
||||
regulator-min-microvolt = <860000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
pwms = <&pwm_cd 1 1148 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@ -112,6 +128,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mali {
|
||||
mali-supply = <&vddee>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vcc_1v8>;
|
||||
@ -143,10 +163,10 @@
|
||||
|
||||
&pwm_cd {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_c1_pins>;
|
||||
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0";
|
||||
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
|
@ -154,6 +154,23 @@
|
||||
vin-supply = <&p5v0>;
|
||||
};
|
||||
|
||||
vddee: regulator-vddee {
|
||||
/* Monolithic Power Systems MP2161 */
|
||||
compatible = "pwm-regulator";
|
||||
|
||||
regulator-name = "VDDEE";
|
||||
regulator-min-microvolt = <860000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
|
||||
vin-supply = <&p5v0>;
|
||||
|
||||
pwms = <&pwm_cd 1 12218 0>;
|
||||
pwm-dutycycle-range = <91 0>;
|
||||
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_rtc: regulator-vdd-rtc {
|
||||
/*
|
||||
* Torex Semiconductor XC6215 configured for a fixed output of
|
||||
@ -173,6 +190,12 @@
|
||||
cpu-supply = <&vcck>;
|
||||
};
|
||||
|
||||
&efuse {
|
||||
ethernet_mac_address: mac@1b4 {
|
||||
reg = <0x1b4 0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
|
||||
@ -183,6 +206,9 @@
|
||||
phy-handle = <ð_phy>;
|
||||
amlogic,tx-delay-ns = <4>;
|
||||
|
||||
nvmem-cells = <ðernet_mac_address>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
@ -276,6 +302,10 @@
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&mali {
|
||||
mali-supply = <&vddee>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vcc_1v8>;
|
||||
@ -308,10 +338,10 @@
|
||||
|
||||
&pwm_cd {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_c1_pins>;
|
||||
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0";
|
||||
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
|
||||
clock-names = "clkin0", "clkin1";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
|
@ -361,6 +361,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_d_pins: pwm-d {
|
||||
mux {
|
||||
groups = "pwm_d";
|
||||
function = "pwm_d";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart_b0_pins: uart-b0 {
|
||||
mux {
|
||||
groups = "uart_tx_b0",
|
||||
@ -410,6 +418,8 @@
|
||||
<&clkc CLKID_MPLL2>,
|
||||
<&clkc CLKID_MPLL2>;
|
||||
clock-names = "stmmaceth", "clkin0", "clkin1";
|
||||
rx-fifo-depth = <4096>;
|
||||
tx-fifo-depth = <2048>;
|
||||
|
||||
resets = <&reset RESET_ETHERNET>;
|
||||
reset-names = "stmmaceth";
|
||||
|
Loading…
Reference in New Issue
Block a user