S2io: Removed unused feature - bimodal interrupts
Removed bimodal interrupt support - unused feature Signed-off-by: Sivakumar Subramani <sivakumar.subramani@neterion.com> Signed-off-by: Ramkrishna Vepa <ram.vepa@neterion.com> Signed-off-by: Jeff Garzik <jeff@garzik.org> [also, trim trailing whitespace]
This commit is contained in:
Sivakumar Subramani
David S. Miller
parent
bd684e43d6
commit
8a4bdbaa93
@ -84,7 +84,7 @@
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#include "s2io.h"
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#include "s2io-regs.h"
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#define DRV_VERSION "2.0.26.2"
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#define DRV_VERSION "2.0.26.4"
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/* S2io Driver name & version. */
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static char s2io_driver_name[] = "Neterion";
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@ -452,7 +452,6 @@ S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
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S2IO_PARM_INT(shared_splits, 0);
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S2IO_PARM_INT(tmac_util_period, 5);
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S2IO_PARM_INT(rmac_util_period, 5);
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S2IO_PARM_INT(bimodal, 0);
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S2IO_PARM_INT(l3l4hdr_size, 128);
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/* Frequency of Rx desc syncs expressed as power of 2 */
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S2IO_PARM_INT(rxsync_frequency, 3);
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@ -1565,90 +1564,57 @@ static int init_nic(struct s2io_nic *nic)
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time++;
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}
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if (nic->config.bimodal) {
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int k = 0;
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for (k = 0; k < config->rx_ring_num; k++) {
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val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
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val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
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writeq(val64, &bar0->tti_command_mem);
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/* RTI Initialization */
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if (nic->device_type == XFRAME_II_DEVICE) {
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/*
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* Programmed to generate Apprx 500 Intrs per
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* second
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*/
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int count = (nic->config.bus_speed * 125)/4;
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
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} else
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
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val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
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RTI_DATA1_MEM_RX_URNG_B(0x10) |
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RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
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writeq(val64, &bar0->rti_data1_mem);
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val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
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RTI_DATA2_MEM_RX_UFC_B(0x2) ;
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if (nic->config.intr_type == MSI_X)
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val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
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RTI_DATA2_MEM_RX_UFC_D(0x40));
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else
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val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
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RTI_DATA2_MEM_RX_UFC_D(0x80));
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writeq(val64, &bar0->rti_data2_mem);
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for (i = 0; i < config->rx_ring_num; i++) {
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val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
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| RTI_CMD_MEM_OFFSET(i);
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writeq(val64, &bar0->rti_command_mem);
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/*
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* Once the operation completes, the Strobe bit of the command
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* register will be reset. We poll for this particular condition
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* We wait for a maximum of 500ms for the operation to complete,
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* if it's not complete by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->tti_command_mem);
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if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG,
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"%s: TTI init Failed\n",
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dev->name);
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return -1;
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}
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time++;
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msleep(50);
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}
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}
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} else {
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/* RTI Initialization */
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if (nic->device_type == XFRAME_II_DEVICE) {
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/*
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* Programmed to generate Apprx 500 Intrs per
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* second
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*/
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int count = (nic->config.bus_speed * 125)/4;
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
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} else {
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val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
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}
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val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
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RTI_DATA1_MEM_RX_URNG_B(0x10) |
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RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
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writeq(val64, &bar0->rti_data1_mem);
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val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
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RTI_DATA2_MEM_RX_UFC_B(0x2) ;
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if (nic->config.intr_type == MSI_X)
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val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
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RTI_DATA2_MEM_RX_UFC_D(0x40));
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else
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val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
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RTI_DATA2_MEM_RX_UFC_D(0x80));
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writeq(val64, &bar0->rti_data2_mem);
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for (i = 0; i < config->rx_ring_num; i++) {
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val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
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| RTI_CMD_MEM_OFFSET(i);
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writeq(val64, &bar0->rti_command_mem);
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/*
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* Once the operation completes, the Strobe bit of the
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* command register will be reset. We poll for this
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* particular condition. We wait for a maximum of 500ms
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* for the operation to complete, if it's not complete
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* by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->rti_command_mem);
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if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
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dev->name);
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return -1;
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}
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time++;
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msleep(50);
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* Once the operation completes, the Strobe bit of the
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* command register will be reset. We poll for this
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* particular condition. We wait for a maximum of 500ms
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* for the operation to complete, if it's not complete
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* by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->rti_command_mem);
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if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
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break;
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if (time > 10) {
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DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
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dev->name);
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return -1;
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}
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time++;
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msleep(50);
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}
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}
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@ -2151,8 +2117,6 @@ static int start_nic(struct s2io_nic *nic)
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&bar0->prc_rxd0_n[i]);
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val64 = readq(&bar0->prc_ctrl_n[i]);
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if (nic->config.bimodal)
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val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
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if (nic->rxd_mode == RXD_MODE_1)
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val64 |= PRC_CTRL_RC_ENABLED;
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else
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@ -3702,27 +3666,15 @@ static int s2io_enable_msi_x(struct s2io_nic *nic)
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}
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writeq(tx_mat, &bar0->tx_mat0_n[0]);
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if (!nic->config.bimodal) {
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rx_mat = readq(&bar0->rx_mat);
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for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
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rx_mat |= RX_MAT_SET(j, msix_indx);
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nic->s2io_entries[msix_indx].arg
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= &nic->mac_control.rings[j];
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nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
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nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
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}
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writeq(rx_mat, &bar0->rx_mat);
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} else {
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tx_mat = readq(&bar0->tx_mat0_n[7]);
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for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
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tx_mat |= TX_MAT_SET(i, msix_indx);
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nic->s2io_entries[msix_indx].arg
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= &nic->mac_control.rings[j];
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nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
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nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
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}
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writeq(tx_mat, &bar0->tx_mat0_n[7]);
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rx_mat = readq(&bar0->rx_mat);
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for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
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rx_mat |= RX_MAT_SET(j, msix_indx);
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nic->s2io_entries[msix_indx].arg
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= &nic->mac_control.rings[j];
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nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
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nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
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}
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writeq(rx_mat, &bar0->rx_mat);
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nic->avail_msix_vectors = 0;
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ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
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@ -7752,14 +7704,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
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/* Initialize device name */
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sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
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/* Initialize bimodal Interrupts */
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sp->config.bimodal = bimodal;
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if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
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sp->config.bimodal = 0;
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DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
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dev->name);
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}
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/*
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* Make Link state as off at this point, when the Link change
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* interrupt comes the state will be automatically changed to
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@ -444,7 +444,6 @@ struct config_param {
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#define MAX_RX_BLOCKS_PER_RING 150
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struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
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u8 bimodal; /*Flag for setting bimodal interrupts*/
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#define HEADER_ETHERNET_II_802_3_SIZE 14
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#define HEADER_802_2_SIZE 3
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