leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

S2io: Removed unused feature - bimodal interrupts

Browse Source 
Removed bimodal interrupt support - unused feature

Signed-off-by: Sivakumar Subramani <sivakumar.subramani@neterion.com>
Signed-off-by: Ramkrishna Vepa <ram.vepa@neterion.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

[also, trim trailing whitespace]
This commit is contained in:
Sivakumar Subramani 2007-09-18 18:14:20 -04:00 committed by David S. Miller
parent bd684e43d6
commit 8a4bdbaa93
2 changed files with 90 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

170
drivers/net/s2io.c
View File

@ -84,7 +84,7 @@
#include "s2io.h" #include "s2io.h"
#include "s2io-regs.h" #include "s2io-regs.h"
#define DRV_VERSION "2.0.26.2" #define DRV_VERSION "2.0.26.4"
/* S2io Driver name & version. */ /* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion"; static char s2io_driver_name[] = "Neterion";
@ -452,7 +452,6 @@ S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
S2IO_PARM_INT(shared_splits, 0); S2IO_PARM_INT(shared_splits, 0);
S2IO_PARM_INT(tmac_util_period, 5); S2IO_PARM_INT(tmac_util_period, 5);
S2IO_PARM_INT(rmac_util_period, 5); S2IO_PARM_INT(rmac_util_period, 5);
S2IO_PARM_INT(bimodal, 0);
S2IO_PARM_INT(l3l4hdr_size, 128); S2IO_PARM_INT(l3l4hdr_size, 128);
/* Frequency of Rx desc syncs expressed as power of 2 */ /* Frequency of Rx desc syncs expressed as power of 2 */
S2IO_PARM_INT(rxsync_frequency, 3); S2IO_PARM_INT(rxsync_frequency, 3);
@ -1565,90 +1564,57 @@ static int init_nic(struct s2io_nic *nic)
time++; time++;
} }
if (nic->config.bimodal) { /* RTI Initialization */
int k = 0; if (nic->device_type == XFRAME_II_DEVICE) {
for (k = 0; k < config->rx_ring_num; k++) { /*
val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; * Programmed to generate Apprx 500 Intrs per
val64 |= TTI_CMD_MEM_OFFSET(0x38+k); * second
writeq(val64, &bar0->tti_command_mem); */
int count = (nic->config.bus_speed * 125)/4;
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
} else
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
RTI_DATA1_MEM_RX_URNG_B(0x10) |
RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
writeq(val64, &bar0->rti_data1_mem);
val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
RTI_DATA2_MEM_RX_UFC_B(0x2) ;
if (nic->config.intr_type == MSI_X)
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
RTI_DATA2_MEM_RX_UFC_D(0x40));
else
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
RTI_DATA2_MEM_RX_UFC_D(0x80));
writeq(val64, &bar0->rti_data2_mem);
for (i = 0; i < config->rx_ring_num; i++) {
val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
| RTI_CMD_MEM_OFFSET(i);
writeq(val64, &bar0->rti_command_mem);
/* /*
* Once the operation completes, the Strobe bit of the command * Once the operation completes, the Strobe bit of the
* register will be reset. We poll for this particular condition * command register will be reset. We poll for this
* We wait for a maximum of 500ms for the operation to complete, * particular condition. We wait for a maximum of 500ms
* if it's not complete by then we return error. * for the operation to complete, if it's not complete
*/ * by then we return error.
time = 0; */
while (TRUE) { time = 0;
val64 = readq(&bar0->tti_command_mem); while (TRUE) {
if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { val64 = readq(&bar0->rti_command_mem);
break; if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
} break;
if (time > 10) {
DBG_PRINT(ERR_DBG, if (time > 10) {
"%s: TTI init Failed\n", DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
dev->name); dev->name);
return -1; return -1;
}
time++;
msleep(50);
}
}
} else {
/* RTI Initialization */
if (nic->device_type == XFRAME_II_DEVICE) {
/*
* Programmed to generate Apprx 500 Intrs per
* second
*/
int count = (nic->config.bus_speed * 125)/4;
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
} else {
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
}
val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
RTI_DATA1_MEM_RX_URNG_B(0x10) |
RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
writeq(val64, &bar0->rti_data1_mem);
val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
RTI_DATA2_MEM_RX_UFC_B(0x2) ;
if (nic->config.intr_type == MSI_X)
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
RTI_DATA2_MEM_RX_UFC_D(0x40));
else
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
RTI_DATA2_MEM_RX_UFC_D(0x80));
writeq(val64, &bar0->rti_data2_mem);
for (i = 0; i < config->rx_ring_num; i++) {
val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
| RTI_CMD_MEM_OFFSET(i);
writeq(val64, &bar0->rti_command_mem);
/*
* Once the operation completes, the Strobe bit of the
* command register will be reset. We poll for this
* particular condition. We wait for a maximum of 500ms
* for the operation to complete, if it's not complete
* by then we return error.
*/
time = 0;
while (TRUE) {
val64 = readq(&bar0->rti_command_mem);
if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
break;
}
if (time > 10) {
DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
dev->name);
return -1;
}
time++;
msleep(50);
} }
time++;
msleep(50);
} }
} }
@ -2151,8 +2117,6 @@ static int start_nic(struct s2io_nic *nic)
&bar0->prc_rxd0_n[i]); &bar0->prc_rxd0_n[i]);
val64 = readq(&bar0->prc_ctrl_n[i]); val64 = readq(&bar0->prc_ctrl_n[i]);
if (nic->config.bimodal)
val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
if (nic->rxd_mode == RXD_MODE_1) if (nic->rxd_mode == RXD_MODE_1)
val64 |= PRC_CTRL_RC_ENABLED; val64 |= PRC_CTRL_RC_ENABLED;
else else
@ -3702,27 +3666,15 @@ static int s2io_enable_msi_x(struct s2io_nic *nic)
} }
writeq(tx_mat, &bar0->tx_mat0_n[0]); writeq(tx_mat, &bar0->tx_mat0_n[0]);
if (!nic->config.bimodal) { rx_mat = readq(&bar0->rx_mat);
rx_mat = readq(&bar0->rx_mat); for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) { rx_mat |= RX_MAT_SET(j, msix_indx);
rx_mat |= RX_MAT_SET(j, msix_indx); nic->s2io_entries[msix_indx].arg
nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
= &nic->mac_control.rings[j]; nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE; nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
}
writeq(rx_mat, &bar0->rx_mat);
} else {
tx_mat = readq(&bar0->tx_mat0_n[7]);
for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
tx_mat |= TX_MAT_SET(i, msix_indx);
nic->s2io_entries[msix_indx].arg
= &nic->mac_control.rings[j];
nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
}
writeq(tx_mat, &bar0->tx_mat0_n[7]);
} }
writeq(rx_mat, &bar0->rx_mat);
nic->avail_msix_vectors = 0; nic->avail_msix_vectors = 0;
ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X); ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
@ -7752,14 +7704,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
/* Initialize device name */ /* Initialize device name */
sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
/* Initialize bimodal Interrupts */
sp->config.bimodal = bimodal;
if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
sp->config.bimodal = 0;
DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
dev->name);
}
/* /*
* Make Link state as off at this point, when the Link change * Make Link state as off at this point, when the Link change
* interrupt comes the state will be automatically changed to * interrupt comes the state will be automatically changed to

1
drivers/net/s2io.h
View File

@ -444,7 +444,6 @@ struct config_param {
#define MAX_RX_BLOCKS_PER_RING 150 #define MAX_RX_BLOCKS_PER_RING 150
struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
u8 bimodal; /*Flag for setting bimodal interrupts*/
#define HEADER_ETHERNET_II_802_3_SIZE 14 #define HEADER_ETHERNET_II_802_3_SIZE 14
#define HEADER_802_2_SIZE 3 #define HEADER_802_2_SIZE 3