forked from Minki/linux
[PATCH] skge: remove XM phy (untested code)
Remove support for the non-Broadcom genesis based boards. The code is untested, and probably won't work as is. The newer boards are all Yukon based, and only old Genesis board I can find uses Broadcom. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
c506a50902
commit
89bf5f231f
@ -621,16 +621,8 @@ static void skge_led_on(struct skge_hw *hw, int port)
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skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
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skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
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switch (hw->phy_type) {
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case SK_PHY_BCOM:
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
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PHY_B_PEC_LED_ON);
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break;
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default:
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skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
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skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
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skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
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}
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/* For Broadcom Phy only */
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
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gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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@ -651,15 +643,8 @@ static void skge_led_off(struct skge_hw *hw, int port)
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skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
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skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
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switch (hw->phy_type) {
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case SK_PHY_BCOM:
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
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PHY_B_PEC_LED_OFF);
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break;
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default:
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skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
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skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
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}
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/* Broadcom only */
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
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gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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@ -887,7 +872,8 @@ static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
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xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
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v = xm_read16(hw, port, XM_PHY_DATA);
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if (hw->phy_type != SK_PHY_XMAC) {
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/* Need to wait for external PHY */
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (xm_read16(hw, port, XM_MMU_CMD)
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@ -900,7 +886,6 @@ static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
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return 0;
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ready:
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v = xm_read16(hw, port, XM_PHY_DATA);
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}
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return v;
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}
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@ -913,7 +898,7 @@ static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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for (i = 0; i < PHY_RETRIES; i++) {
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if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
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goto ready;
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cpu_relax();
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udelay(1);
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}
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printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
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hw->dev[port]->name);
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@ -970,8 +955,7 @@ static void genesis_reset(struct skge_hw *hw, int port)
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xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
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xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
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/* disable all PHY IRQs */
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if (hw->phy_type == SK_PHY_BCOM)
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/* disable Broadcom PHY IRQ */
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xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
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xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
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@ -1020,7 +1004,8 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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* GMII mode.
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*/
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spin_lock_bh(&hw->phy_lock);
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if (hw->phy_type != SK_PHY_XMAC) {
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/* External Phy Handling */
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/* Take PHY out of reset. */
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r = skge_read32(hw, B2_GP_IO);
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if (port == 0)
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@ -1066,7 +1051,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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*/
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r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
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}
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/* Dummy read */
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xm_read16(hw, port, XM_ISRC);
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@ -1150,38 +1135,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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else
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xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
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switch (hw->phy_type) {
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case SK_PHY_XMAC:
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if (skge->autoneg == AUTONEG_ENABLE) {
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ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
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switch (skge->flow_control) {
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case FLOW_MODE_NONE:
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ctrl1 |= PHY_X_P_NO_PAUSE;
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break;
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case FLOW_MODE_LOC_SEND:
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ctrl1 |= PHY_X_P_ASYM_MD;
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break;
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case FLOW_MODE_SYMMETRIC:
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ctrl1 |= PHY_X_P_SYM_MD;
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break;
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case FLOW_MODE_REM_SEND:
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ctrl1 |= PHY_X_P_BOTH_MD;
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break;
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}
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xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
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ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
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} else {
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ctrl2 = 0;
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if (skge->duplex == DUPLEX_FULL)
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ctrl2 |= PHY_CT_DUP_MD;
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}
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xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
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break;
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case SK_PHY_BCOM:
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/* Broadcom phy initialization */
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ctrl1 = PHY_CT_SP1000;
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ctrl2 = 0;
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ctrl3 = PHY_AN_CSMA;
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@ -1237,8 +1191,6 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
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break;
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}
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spin_unlock_bh(&hw->phy_lock);
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/* Clear MIB counters */
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@ -1256,6 +1208,7 @@ static void genesis_stop(struct skge_port *skge)
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{
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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u32 reg;
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/* Clear Tx packet arbiter timeout IRQ */
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skge_write16(hw, B3_PA_CTRL,
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@ -1273,9 +1226,7 @@ static void genesis_stop(struct skge_port *skge)
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skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
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/* For external PHYs there must be special handling */
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if (hw->phy_type != SK_PHY_XMAC) {
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u32 reg = skge_read32(hw, B2_GP_IO);
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reg = skge_read32(hw, B2_GP_IO);
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if (port == 0) {
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reg |= GP_DIR_0;
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reg &= ~GP_IO_0;
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@ -1285,7 +1236,6 @@ static void genesis_stop(struct skge_port *skge)
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}
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skge_write32(hw, B2_GP_IO, reg);
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skge_read32(hw, B2_GP_IO);
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}
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xm_write16(hw, port, XM_MMU_CMD,
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xm_read16(hw, port, XM_MMU_CMD)
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@ -1329,16 +1279,6 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
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u16 status = xm_read16(hw, port, XM_ISRC);
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pr_debug("genesis_intr status %x\n", status);
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if (hw->phy_type == SK_PHY_XMAC) {
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/* LInk down, start polling for state change */
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if (status & XM_IS_INP_ASS) {
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xm_write16(hw, port, XM_IMSK,
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xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
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mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
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}
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else if (status & XM_IS_AND)
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mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
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}
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if (status & XM_IS_TXF_UR) {
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xm_write32(hw, port, XM_MODE, XM_MD_FTF);
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@ -1458,18 +1398,17 @@ static void genesis_link_up(struct skge_port *skge)
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xm_write32(hw, port, XM_MODE, mode);
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msk = XM_DEF_MSK;
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if (hw->phy_type != SK_PHY_XMAC)
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msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
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/* disable GP0 interrupt bit for external Phy */
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msk |= XM_IS_INP_ASS;
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xm_write16(hw, port, XM_IMSK, msk);
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xm_read16(hw, port, XM_ISRC);
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/* get MMU Command Reg. */
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cmd = xm_read16(hw, port, XM_MMU_CMD);
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if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
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if (skge->duplex == DUPLEX_FULL)
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cmd |= XM_MMU_GMII_FD;
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if (hw->phy_type == SK_PHY_BCOM) {
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/*
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* Workaround BCOM Errata (#10523) for all BCom Phys
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* Enable Power Management after link up
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@ -1477,9 +1416,7 @@ static void genesis_link_up(struct skge_port *skge)
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
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xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
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& ~PHY_B_AC_DIS_PM);
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xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
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PHY_B_DEF_MSK);
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}
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xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
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/* enable Rx/Tx */
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xm_write16(hw, port, XM_MMU_CMD,
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@ -1551,25 +1488,12 @@ static void skge_link_timer(unsigned long __arg)
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{
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struct skge_port *skge = (struct skge_port *) __arg;
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
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return;
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spin_lock_bh(&hw->phy_lock);
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if (hw->phy_type == SK_PHY_BCOM)
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genesis_bcom_intr(skge);
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else {
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int i;
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for (i = 0; i < 3; i++)
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if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
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break;
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if (i == 3)
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mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
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else
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genesis_link_up(skge);
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}
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spin_unlock_bh(&hw->phy_lock);
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}
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@ -2737,7 +2661,7 @@ static void skge_extirq(unsigned long data)
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if (hw->chip_id != CHIP_ID_GENESIS)
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yukon_phy_intr(skge);
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else if (hw->phy_type == SK_PHY_BCOM)
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else
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genesis_bcom_intr(skge);
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}
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}
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@ -2886,9 +2810,6 @@ static int skge_reset(struct skge_hw *hw)
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switch (hw->chip_id) {
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case CHIP_ID_GENESIS:
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switch (hw->phy_type) {
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case SK_PHY_XMAC:
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hw->phy_addr = PHY_ADDR_XMAC;
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break;
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case SK_PHY_BCOM:
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hw->phy_addr = PHY_ADDR_BCOM;
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break;
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