clk: sunxi-ng: mux: Rename mux macro to be consistent
Rename the internal mux macro to be consistent with the other internal structure macros. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -83,7 +83,7 @@ struct ccu_div {
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struct ccu_div _struct = { \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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@ -44,7 +44,7 @@ struct ccu_mp {
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.enable = _gate, \
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.enable = _gate, \
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
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.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
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.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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@ -21,7 +21,7 @@ struct ccu_mux_internal {
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} variable_prediv;
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} variable_prediv;
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};
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};
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#define SUNXI_CLK_MUX(_shift, _width) \
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#define _SUNXI_CCU_MUX(_shift, _width) \
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{ \
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{ \
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.shift = _shift, \
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.shift = _shift, \
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.width = _width, \
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.width = _width, \
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@ -37,7 +37,7 @@ struct ccu_mux {
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#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, _flags) \
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#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, _flags) \
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struct ccu_mux _struct = { \
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struct ccu_mux _struct = { \
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.mux = SUNXI_CLK_MUX(_shift, _width), \
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.mux = _SUNXI_CCU_MUX(_shift, _width), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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@ -51,7 +51,7 @@ struct ccu_mux {
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_shift, _width, _gate, _flags) \
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_shift, _width, _gate, _flags) \
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struct ccu_mux _struct = { \
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struct ccu_mux _struct = { \
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.enable = _gate, \
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.enable = _gate, \
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.mux = SUNXI_CLK_MUX(_shift, _width), \
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.mux = _SUNXI_CCU_MUX(_shift, _width), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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@ -49,7 +49,7 @@ struct ccu_nkm {
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.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
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.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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