irqchip: renesas-intc-irqpin: DT binding for sense bitfield width

Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to optionally
specify such non-standard values.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Guennadi Liakhovetski 2013-06-13 11:23:38 +02:00 committed by Simon Horman
parent 24603f3caf
commit 894db16426
2 changed files with 18 additions and 0 deletions

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@ -0,0 +1,14 @@
DT bindings for the R-/SH-Mobile irqpin controller
Required properties:
- compatible: has to be "renesas,intc-irqpin"
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
Optional properties:
- any properties, listed in interrupts.txt, and any standard resource allocation
properties
- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
if different from the default 4 bits

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@ -18,6 +18,7 @@
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device *pdev)
/* deal with driver instance configuration */
if (pdata)
memcpy(&p->config, pdata, sizeof(*pdata));
else
of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
&p->config.sense_bitfield_width);
if (!p->config.sense_bitfield_width)
p->config.sense_bitfield_width = 4; /* default to 4 bits */