forked from Minki/linux
drm/mgag200: Convert to simple KMS helper
The mgag200 supports a single pipeline with only a primary plane. It can be converted to simple KMS helpers. This also adds support for atomic modesetting. Wayland compositors, which use pageflip ioctls, can now be used with mgag200. v2: * prepare encoder and CRTC in a separate patch * remove suspend/resume code in a separate patch * don't call set_format_regs() in pipe_update() Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Tested-by: John Donnelly <John.p.donnelly@oracle.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Emil Velikov <emil.velikov@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-15-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
parent
f05c9e1309
commit
88fabb75ea
@ -140,7 +140,7 @@ int mgag200_driver_dumb_create(struct drm_file *file,
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}
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static struct drm_driver driver = {
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.driver_features = DRIVER_GEM | DRIVER_MODESET,
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.driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
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.fops = &mgag200_driver_fops,
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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@ -11,10 +11,13 @@
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_atomic_state_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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@ -30,13 +33,18 @@ static void mga_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_framebuffer *fb;
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u16 *r_ptr, *g_ptr, *b_ptr;
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int i;
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if (!crtc->enabled)
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return;
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if (!mdev->display_pipe.plane.state)
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return;
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fb = mdev->display_pipe.plane.state->fb;
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r_ptr = crtc->gamma_store;
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g_ptr = r_ptr + crtc->gamma_size;
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b_ptr = g_ptr + crtc->gamma_size;
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@ -869,56 +877,6 @@ static void mgag200_set_startadd(struct mga_device *mdev,
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WREG_ECRT(0x00, crtcext0);
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}
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static int mga_crtc_do_set_base(struct mga_device *mdev,
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const struct drm_framebuffer *fb,
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const struct drm_framebuffer *old_fb)
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{
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struct drm_gem_vram_object *gbo;
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int ret;
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s64 gpu_addr;
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if (old_fb) {
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gbo = drm_gem_vram_of_gem(old_fb->obj[0]);
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drm_gem_vram_unpin(gbo);
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}
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gbo = drm_gem_vram_of_gem(fb->obj[0]);
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ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
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if (ret)
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return ret;
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gpu_addr = drm_gem_vram_offset(gbo);
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if (gpu_addr < 0) {
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ret = (int)gpu_addr;
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goto err_drm_gem_vram_unpin;
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}
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mgag200_set_startadd(mdev, (unsigned long)gpu_addr);
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return 0;
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err_drm_gem_vram_unpin:
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drm_gem_vram_unpin(gbo);
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return ret;
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}
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static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = dev->dev_private;
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struct drm_framebuffer *fb = crtc->primary->fb;
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unsigned int count;
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do { } while (RREG8(0x1fda) & 0x08);
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do { } while (!(RREG8(0x1fda) & 0x08));
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count = RREG8(MGAREG_VCOUNT) + 2;
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do { } while (RREG8(MGAREG_VCOUNT) < count);
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return mga_crtc_do_set_base(mdev, fb, old_fb);
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}
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static void mgag200_set_pci_regs(struct mga_device *mdev)
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{
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uint32_t option = 0, option2 = 0;
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@ -1329,34 +1287,6 @@ static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
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WREG_ECRT(0x06, 0x00);
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}
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static int mga_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y, struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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const struct drm_framebuffer *fb = crtc->primary->fb;
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mgag200_init_regs(mdev);
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mgag200_set_format_regs(mdev, fb);
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mga_crtc_do_set_base(mdev, fb, old_fb);
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mgag200_set_offset(mdev, fb);
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mgag200_set_mode_regs(mdev, mode);
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if (mdev->type == G200_ER)
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mgag200_g200er_reset_tagfifo(mdev);
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if (IS_G200_SE(mdev))
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mgag200_g200se_set_hiprilvl(mdev, mode, fb);
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else if (mdev->type == G200_EV)
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mgag200_g200ev_set_hiprilvl(mdev);
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return 0;
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}
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static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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@ -1439,7 +1369,6 @@ static void mga_crtc_commit(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
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u8 tmp;
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if (mdev->type == G200_WB || mdev->type == G200_EW3)
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@ -1458,63 +1387,7 @@ static void mga_crtc_commit(struct drm_crtc *crtc)
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WREG_SEQ(0x1, tmp);
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WREG_SEQ(0, 3);
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}
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crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
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}
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/*
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* The core can pass us a set of gamma values to program. We actually only
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* use this for 8-bit mode so can't perform smooth fades on deeper modes,
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* but it's a requirement that we provide the function
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*/
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static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, uint32_t size,
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struct drm_modeset_acquire_ctx *ctx)
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{
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mga_crtc_load_lut(crtc);
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return 0;
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}
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static void mga_crtc_disable(struct drm_crtc *crtc)
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{
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DRM_DEBUG_KMS("\n");
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mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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if (crtc->primary->fb) {
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struct drm_framebuffer *fb = crtc->primary->fb;
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struct drm_gem_vram_object *gbo =
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drm_gem_vram_of_gem(fb->obj[0]);
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drm_gem_vram_unpin(gbo);
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}
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crtc->primary->fb = NULL;
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}
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/* These provide the minimum set of functions required to handle a CRTC */
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static const struct drm_crtc_funcs mga_crtc_funcs = {
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.gamma_set = mga_crtc_gamma_set,
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.set_config = drm_crtc_helper_set_config,
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.destroy = drm_crtc_cleanup,
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};
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static const struct drm_crtc_helper_funcs mga_helper_funcs = {
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.disable = mga_crtc_disable,
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.dpms = mga_crtc_dpms,
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.mode_set = mga_crtc_mode_set,
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.mode_set_base = mga_crtc_mode_set_base,
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.prepare = mga_crtc_prepare,
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.commit = mga_crtc_commit,
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};
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/* CRTC setup */
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static void mga_crtc_init(struct mga_device *mdev)
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{
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struct drm_device *dev = mdev->dev;
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struct drm_crtc *crtc = &mdev->display_pipe.crtc;
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drm_crtc_init(dev, crtc, &mga_crtc_funcs);
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drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE);
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drm_crtc_helper_add(crtc, &mga_helper_funcs);
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mga_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
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}
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/*
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@ -1653,9 +1526,11 @@ static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs =
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};
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static const struct drm_connector_funcs mga_vga_connector_funcs = {
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.dpms = drm_helper_connector_dpms,
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.reset = drm_atomic_helper_connector_reset,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = mga_connector_destroy,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static int mgag200_vga_connector_init(struct mga_device *mdev)
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@ -1687,8 +1562,137 @@ err_mgag200_i2c_destroy:
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return ret;
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}
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/*
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* Simple Display Pipe
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*/
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static enum drm_mode_status
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mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
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const struct drm_display_mode *mode)
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{
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return MODE_OK;
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}
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static void
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mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
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struct drm_crtc_state *crtc_state,
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struct drm_plane_state *plane_state)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
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struct drm_framebuffer *fb = plane_state->fb;
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struct drm_gem_vram_object *gbo;
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s64 gpu_addr;
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gbo = drm_gem_vram_of_gem(fb->obj[0]);
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gpu_addr = drm_gem_vram_offset(gbo);
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if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
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return; /* BUG: BO should have been pinned to VRAM. */
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mga_crtc_prepare(crtc);
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mgag200_set_format_regs(mdev, fb);
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mgag200_set_mode_regs(mdev, adjusted_mode);
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if (mdev->type == G200_ER)
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mgag200_g200er_reset_tagfifo(mdev);
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if (IS_G200_SE(mdev))
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mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
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else if (mdev->type == G200_EV)
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mgag200_g200ev_set_hiprilvl(mdev);
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mga_crtc_commit(crtc);
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}
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static void
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mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
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{
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struct drm_crtc *crtc = &pipe->crtc;
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mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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static int
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mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *plane_state,
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struct drm_crtc_state *crtc_state)
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{
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struct drm_plane *plane = plane_state->plane;
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struct drm_framebuffer *new_fb = plane_state->fb;
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struct drm_framebuffer *fb = NULL;
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if (!new_fb)
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return 0;
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if (plane->state)
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fb = plane->state->fb;
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if (!fb || (fb->format != new_fb->format))
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crtc_state->mode_changed = true; /* update PLL settings */
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return 0;
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}
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static void
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mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
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struct drm_plane_state *old_state)
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{
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struct drm_plane *plane = &pipe->plane;
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struct drm_device *dev = plane->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_vram_object *gbo;
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s64 gpu_addr;
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if (!fb)
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return;
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gbo = drm_gem_vram_of_gem(fb->obj[0]);
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gpu_addr = drm_gem_vram_offset(gbo);
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if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
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return; /* BUG: BO should have been pinned to VRAM. */
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mgag200_set_startadd(mdev, (unsigned long)gpu_addr);
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mgag200_set_offset(mdev, fb);
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}
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static const struct drm_simple_display_pipe_funcs
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mgag200_simple_display_pipe_funcs = {
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.mode_valid = mgag200_simple_display_pipe_mode_valid,
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.enable = mgag200_simple_display_pipe_enable,
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.disable = mgag200_simple_display_pipe_disable,
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.check = mgag200_simple_display_pipe_check,
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.update = mgag200_simple_display_pipe_update,
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.prepare_fb = drm_gem_vram_simple_display_pipe_prepare_fb,
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.cleanup_fb = drm_gem_vram_simple_display_pipe_cleanup_fb,
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};
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static const uint32_t mgag200_simple_display_pipe_formats[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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};
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static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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/*
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* Mode config
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*/
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static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
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.fb_create = drm_gem_fb_create
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.fb_create = drm_gem_fb_create,
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.mode_valid = drm_vram_helper_mode_valid,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
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@ -1702,8 +1706,9 @@ static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
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int mgag200_modeset_init(struct mga_device *mdev)
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{
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struct drm_device *dev = mdev->dev;
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struct drm_encoder *encoder = &mdev->display_pipe.encoder;
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struct drm_connector *connector = &mdev->connector.base;
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struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
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size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
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int ret;
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mdev->bpp_shifts[0] = 0;
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@ -1711,6 +1716,8 @@ int mgag200_modeset_init(struct mga_device *mdev)
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mdev->bpp_shifts[2] = 0;
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mdev->bpp_shifts[3] = 2;
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mgag200_init_regs(mdev);
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ret = drmm_mode_config_init(dev);
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if (ret) {
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drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
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@ -1728,17 +1735,6 @@ int mgag200_modeset_init(struct mga_device *mdev)
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dev->mode_config.funcs = &mgag200_mode_config_funcs;
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mga_crtc_init(mdev);
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ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
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if (ret) {
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drm_err(dev,
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"drm_simple_encoder_init() failed, error %d\n",
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ret);
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return ret;
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}
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encoder->possible_crtcs = 0x1;
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ret = mgag200_vga_connector_init(mdev);
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if (ret) {
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drm_err(dev,
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@ -1747,7 +1743,23 @@ int mgag200_modeset_init(struct mga_device *mdev)
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return ret;
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}
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drm_connector_attach_encoder(connector, encoder);
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ret = drm_simple_display_pipe_init(dev, pipe,
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&mgag200_simple_display_pipe_funcs,
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mgag200_simple_display_pipe_formats,
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format_count,
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mgag200_simple_display_pipe_fmtmods,
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connector);
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if (ret) {
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drm_err(dev,
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"drm_simple_display_pipe_init() failed, error %d\n",
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ret);
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return ret;
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}
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/* FIXME: legacy gamma tables; convert to CRTC state */
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drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
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drm_mode_config_reset(dev);
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return 0;
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}
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