forked from Minki/linux
clk: tegra: cclk_lp has a pllx/2 divider
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
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ARRAY_SIZE(cclk_lp_parents),
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CLK_SET_RATE_PARENT,
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clk_base + CCLKLP_BURST_POLICY,
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0, 4, 8, 9, NULL);
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TEGRA_DIVIDER_2, 4, 8, 9, NULL);
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*dt_clk = clk;
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}
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