net: hns3: Updates MSI/MSI-X alloc/free APIs(depricated) to new APIs
This patch migrates the HNS3 driver code from use of depricated PCI MSI/MSI-X interrupt vector allocation/free APIs to new common APIs. Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Salil Mehta
David S. Miller
parent
97438abcfb
commit
887c3820a3
@ -891,14 +891,14 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
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hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
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if (hnae3_dev_roce_supported(hdev)) {
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hdev->num_roce_msix =
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hdev->num_roce_msi =
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hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
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HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
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/* PF should have NIC vectors and Roce vectors,
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* NIC vectors are queued before Roce vectors.
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*/
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hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
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hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
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} else {
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hdev->num_msi =
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hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
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@ -1950,7 +1950,7 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
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struct hnae3_handle *roce = &vport->roce;
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struct hnae3_handle *nic = &vport->nic;
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roce->rinfo.num_vectors = vport->back->num_roce_msix;
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roce->rinfo.num_vectors = vport->back->num_roce_msi;
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if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
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vport->back->num_msi_left == 0)
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@ -1968,68 +1968,48 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
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return 0;
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}
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static int hclge_init_msix(struct hclge_dev *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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int ret, i;
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hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
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sizeof(struct msix_entry),
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GFP_KERNEL);
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if (!hdev->msix_entries)
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return -ENOMEM;
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hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
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sizeof(u16), GFP_KERNEL);
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if (!hdev->vector_status)
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return -ENOMEM;
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for (i = 0; i < hdev->num_msi; i++) {
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hdev->msix_entries[i].entry = i;
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hdev->vector_status[i] = HCLGE_INVALID_VPORT;
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}
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hdev->num_msi_left = hdev->num_msi;
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hdev->base_msi_vector = hdev->pdev->irq;
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hdev->roce_base_vector = hdev->base_msi_vector +
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HCLGE_ROCE_VECTOR_OFFSET;
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ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
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hdev->num_msi, hdev->num_msi);
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if (ret < 0) {
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dev_info(&hdev->pdev->dev,
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"MSI-X vector alloc failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int hclge_init_msi(struct hclge_dev *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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int vectors;
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int i;
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hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
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sizeof(u16), GFP_KERNEL);
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if (!hdev->vector_status)
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return -ENOMEM;
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for (i = 0; i < hdev->num_msi; i++)
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hdev->vector_status[i] = HCLGE_INVALID_VPORT;
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vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
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vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
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PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (vectors < 0) {
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dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
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return -EINVAL;
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dev_err(&pdev->dev,
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"failed(%d) to allocate MSI/MSI-X vectors\n",
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vectors);
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return vectors;
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}
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if (vectors < hdev->num_msi)
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dev_warn(&hdev->pdev->dev,
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"requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
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hdev->num_msi, vectors);
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hdev->num_msi = vectors;
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hdev->num_msi_left = vectors;
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hdev->base_msi_vector = pdev->irq;
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hdev->roce_base_vector = hdev->base_msi_vector +
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HCLGE_ROCE_VECTOR_OFFSET;
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hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
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sizeof(u16), GFP_KERNEL);
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if (!hdev->vector_status) {
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pci_free_irq_vectors(pdev);
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return -ENOMEM;
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}
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for (i = 0; i < hdev->num_msi; i++)
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hdev->vector_status[i] = HCLGE_INVALID_VPORT;
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hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
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sizeof(int), GFP_KERNEL);
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if (!hdev->vector_irq) {
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pci_free_irq_vectors(pdev);
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return -ENOMEM;
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}
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return 0;
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}
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@ -2704,6 +2684,7 @@ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
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vport->vport_id *
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HCLGE_VECTOR_VF_OFFSET;
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hdev->vector_status[i] = vport->vport_id;
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hdev->vector_irq[i] = vector->vector;
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vector++;
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alloc++;
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@ -2722,15 +2703,10 @@ static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
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{
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int i;
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for (i = 0; i < hdev->num_msi; i++) {
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if (hdev->msix_entries) {
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if (vector == hdev->msix_entries[i].vector)
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return i;
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} else {
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if (vector == (hdev->base_msi_vector + i))
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return i;
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}
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}
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for (i = 0; i < hdev->num_msi; i++)
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if (vector == hdev->vector_irq[i])
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return i;
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return -EINVAL;
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}
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@ -4664,14 +4640,7 @@ static void hclge_pci_uninit(struct hclge_dev *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
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pci_disable_msix(pdev);
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devm_kfree(&pdev->dev, hdev->msix_entries);
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hdev->msix_entries = NULL;
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} else {
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pci_disable_msi(pdev);
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}
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pci_free_irq_vectors(pdev);
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pci_clear_master(pdev);
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pci_release_mem_regions(pdev);
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pci_disable_device(pdev);
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@ -4689,7 +4658,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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goto err_hclge_dev;
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}
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hdev->flag |= HCLGE_FLAG_USE_MSIX;
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hdev->pdev = pdev;
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hdev->ae_dev = ae_dev;
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hdev->reset_type = HNAE3_NONE_RESET;
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@ -4726,12 +4694,9 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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return ret;
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}
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if (hdev->flag & HCLGE_FLAG_USE_MSIX)
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ret = hclge_init_msix(hdev);
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else
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ret = hclge_init_msi(hdev);
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ret = hclge_init_msi(hdev);
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if (ret) {
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dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
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dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
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return ret;
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}
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@ -425,9 +425,6 @@ struct hclge_dev {
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u16 num_tqps; /* Num task queue pairs of this PF */
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u16 num_req_vfs; /* Num VFs requested for this PF */
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u16 num_roce_msix; /* Num of roce vectors for this PF */
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int roce_base_vector;
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/* Base task tqp physical id of this PF */
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u16 base_tqp_pid;
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u16 alloc_rss_size; /* Allocated RSS task queue */
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@ -457,8 +454,10 @@ struct hclge_dev {
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u16 num_msi_left;
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u16 num_msi_used;
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u32 base_msi_vector;
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struct msix_entry *msix_entries;
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u16 *vector_status;
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int *vector_irq;
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u16 num_roce_msi; /* Num of roce vectors for this PF */
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int roce_base_vector;
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u16 pending_udp_bitmap;
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@ -482,12 +481,10 @@ struct hclge_dev {
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struct hnae3_client *nic_client;
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struct hnae3_client *roce_client;
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#define HCLGE_FLAG_USE_MSI 0x00000001
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#define HCLGE_FLAG_USE_MSIX 0x00000002
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#define HCLGE_FLAG_MAIN 0x00000004
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#define HCLGE_FLAG_DCB_CAPABLE 0x00000008
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#define HCLGE_FLAG_DCB_ENABLE 0x00000010
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#define HCLGE_FLAG_MQPRIO_ENABLE 0x00000020
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#define HCLGE_FLAG_MAIN BIT(0)
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#define HCLGE_FLAG_DCB_CAPABLE BIT(1)
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#define HCLGE_FLAG_DCB_ENABLE BIT(2)
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#define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
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u32 flag;
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u32 pkt_buf_size; /* Total pf buf size for tx/rx */
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