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Renesas ARM Based SoC DT Updates for v4.12

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Cleanup:
 * Drop superfluous status update for frequency override on various boards
 * Always use status "okay" to enable devices on porger board
 * Add INTC-SYS clock to device tree of various SoCs
 * Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
 * Remove unit-address and reg from integrated cache on various SoCs
 * Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
 * Fix SCIFB0 dmas indentation on r8a774[35] SoCs
 
 Enhancements:
 * Add watchdog timer to r7s72100 SoC
 * Update sdhi clock bindings on r7s72100 SoC
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Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.12

Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs

Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC

* tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
  ARM: dts: silk: Drop superfluous status update for frequency override
  ARM: dts: alt: Drop superfluous status update for frequency override
  ARM: dts: gose: Drop superfluous status update for frequency override
  ARM: dts: porter: Drop superfluous status update for frequency override
  ARM: dts: koelsch: Drop superfluous status updates for frequency overrides
  ARM: dts: lager: Drop superfluous status update for frequency override
  ARM: dts: marzen: Drop superfluous status update for frequency override
  ARM: dts: bockw: Drop superfluous status update for frequency override
  ARM: dts: porter: Always use status "okay" to enable devices
  ARM: dts: r8a7793: Add INTC-SYS clock to device tree
  ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7794: Add INTC-SYS clock to device tree
  ARM: dts: r8a7792: Add INTC-SYS clock to device tree
  ARM: dts: r8a7791: Add INTC-SYS clock to device tree
  ARM: dts: r8a7790: Add INTC-SYS clock to device tree
  ARM: dts: r8a73a4: Add INTC-SYS clock to device tree
  ARM: dts: r7s72100: Add watchdog timer
  ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-03-21 17:35:06 -07:00
commit 8855e14d61
25 changed files with 113 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
arch/arm/boot/dts/Makefile
View File

@ -679,6 +679,25 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-eb-a9mp-bbrevd.dtb \ arm-realview-eb-a9mp-bbrevd.dtb \
arm-realview-pba8.dtb \ arm-realview-pba8.dtb \
arm-realview-pbx-a9.dtb arm-realview-pbx-a9.dtb
dtb-$(CONFIG_ARCH_RENESAS) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
r8a7792-wheat.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk1108-evb.dtb \ rk1108-evb.dtb \
rk3036-evb.dtb \ rk3036-evb.dtb \
@ -719,25 +738,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-smdkc110.dtb \ s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \ s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
r8a7792-wheat.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \ socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_nand.dtb \

24
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -162,9 +162,12 @@
#clock-cells = <1>; #clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0444 4>; reg = <0xfcfe0444 4>;
clocks = <&p1_clk>, <&p1_clk>; clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; clock-indices = <
clock-output-names = "sdhi1", "sdhi0"; R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
>;
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
}; };
}; };
@ -368,6 +371,13 @@
<0xe8202000 0x1000>; <0xe8202000 0x1000>;
}; };
wdt: watchdog@fcfe0000 {
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
reg = <0xfcfe0000 0x6>;
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
clocks = <&p0_clk>;
};
i2c0: i2c@fcfee000 { i2c0: i2c@fcfee000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -488,7 +498,9 @@
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
clock-names = "core", "cd";
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
@ -501,7 +513,9 @@
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
clock-names = "core", "cd";
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";

19
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -32,18 +32,16 @@
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
clocks = <&cpg_clocks R8A73A4_CLK_Z>; clocks = <&cpg_clocks R8A73A4_CLK_Z>;
power-domains = <&pd_a3sm>; power-domains = <&pd_a3sm>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
L2_CA7: cache-controller@100 { L2_CA7: cache-controller-1 {
compatible = "cache"; compatible = "cache";
reg = <0x100>;
clocks = <&cpg_clocks R8A73A4_CLK_Z2>; clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
power-domains = <&pd_a3km>; power-domains = <&pd_a3km>;
cache-unified; cache-unified;
@ -469,6 +467,9 @@
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&pd_c4>;
}; };
bsc: bus@fec10000 { bsc: bus@fec10000 {
@ -727,16 +728,18 @@
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&main_div2_clk>, <&main_div2_clk>, clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
<&main_div2_clk>,
<&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>,
<&cpg_clocks R8A73A4_CLK_HP>; <&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
R8A73A4_CLK_IIC3
>; >;
clock-output-names = clock-output-names =
"irqc", "iic5", "iic4", "iic3"; "irqc", "intc-sys", "iic5", "iic4", "iic3";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";

5
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -32,9 +32,8 @@
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
power-domains = <&sysc R8A7743_PD_CA15_SCU>; power-domains = <&sysc R8A7743_PD_CA15_SCU>;
@ -277,7 +276,7 @@
clocks = <&cpg CPG_MOD 206>; clocks = <&cpg CPG_MOD 206>;
clock-names = "fck"; clock-names = "fck";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
<&dmac1 0x3d>, <&dmac1 0x3e>; <&dmac1 0x3d>, <&dmac1 0x3e>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";

5
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -32,9 +32,8 @@
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
L2_CA7: cache-controller@0 { L2_CA7: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
power-domains = <&sysc R8A7745_PD_CA7_SCU>; power-domains = <&sysc R8A7745_PD_CA7_SCU>;
@ -277,7 +276,7 @@
clocks = <&cpg CPG_MOD 206>; clocks = <&cpg CPG_MOD 206>;
clock-names = "fck"; clock-names = "fck";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
<&dmac1 0x3d>, <&dmac1 0x3e>; <&dmac1 0x3d>, <&dmac1 0x3e>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";

1
arch/arm/boot/dts/r8a7778-bockw.dts
View File

@ -229,5 +229,4 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };

1
arch/arm/boot/dts/r8a7779-marzen.dts
View File

@ -236,7 +236,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&sdhi0 { &sdhi0 {

1
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -581,7 +581,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&msiof1 { &msiof1 {

19
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -129,17 +129,15 @@
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7790_PD_CA15_SCU>; power-domains = <&sysc R8A7790_PD_CA15_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
L2_CA7: cache-controller@100 { L2_CA7: cache-controller-1 {
compatible = "cache"; compatible = "cache";
reg = <0x100>;
power-domains = <&sysc R8A7790_PD_CA7_SCU>; power-domains = <&sysc R8A7790_PD_CA7_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
@ -187,6 +185,9 @@
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
}; };
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
@ -1366,10 +1367,10 @@
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>; clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7790_CLK_IRQC>; clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;
clock-output-names = "irqc"; clock-output-names = "irqc", "intc-sys";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@ -1740,11 +1741,11 @@
rcar_sound,dvc { rcar_sound,dvc {
dvc0: dvc-0 { dvc0: dvc-0 {
dmas = <&audma0 0xbc>; dmas = <&audma1 0xbc>;
dma-names = "tx"; dma-names = "tx";
}; };
dvc1: dvc-1 { dvc1: dvc-1 {
dmas = <&audma0 0xbe>; dmas = <&audma1 0xbe>;
dma-names = "tx"; dma-names = "tx";
}; };
}; };

2
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -516,7 +516,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&sdhi0 { &sdhi0 {
@ -767,7 +766,6 @@
&pcie_bus_clk { &pcie_bus_clk {
clock-frequency = <100000000>; clock-frequency = <100000000>;
status = "okay";
}; };
&pciec { &pciec {

5
arch/arm/boot/dts/r8a7791-porter.dts
View File

@ -226,7 +226,7 @@
phy-handle = <&phy1>; phy-handle = <&phy1>;
renesas,ether-link-active-low; renesas,ether-link-active-low;
status = "ok"; status = "okay";
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
@ -359,7 +359,7 @@
/* composite video input */ /* composite video input */
&vin0 { &vin0 {
status = "ok"; status = "okay";
pinctrl-0 = <&vin0_pins>; pinctrl-0 = <&vin0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -401,7 +401,6 @@
&pcie_bus_clk { &pcie_bus_clk {
clock-frequency = <100000000>; clock-frequency = <100000000>;
status = "okay";
}; };
&pciec { &pciec {

16
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -74,9 +74,8 @@
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7791_PD_CA15_SCU>; power-domains = <&sysc R8A7791_PD_CA15_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
@ -118,6 +117,9 @@
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
}; };
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
@ -1366,10 +1368,10 @@
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>; clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7791_CLK_IRQC>; clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>;
clock-output-names = "irqc"; clock-output-names = "irqc", "intc-sys";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@ -1777,11 +1779,11 @@
rcar_sound,dvc { rcar_sound,dvc {
dvc0: dvc-0 { dvc0: dvc-0 {
dmas = <&audma0 0xbc>; dmas = <&audma1 0xbc>;
dma-names = "tx"; dma-names = "tx";
}; };
dvc1: dvc-1 { dvc1: dvc-1 {
dmas = <&audma0 0xbe>; dmas = <&audma1 0xbe>;
dma-names = "tx"; dma-names = "tx";
}; };
}; };

14
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -60,9 +60,8 @@
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
power-domains = <&sysc R8A7792_PD_CA15_SCU>; power-domains = <&sysc R8A7792_PD_CA15_SCU>;
@ -93,6 +92,9 @@
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>; IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
}; };
irqc: interrupt-controller@e61c0000 { irqc: interrupt-controller@e61c0000 {
@ -896,10 +898,12 @@
compatible = "renesas,r8a7792-mstp-clocks", compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks"; "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>; clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7792_CLK_IRQC>; clock-indices = <
clock-output-names = "irqc"; R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS
>;
clock-output-names = "irqc", "intc-sys";
}; };
mstp7_clks: mstp7_clks@e615014c { mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7792-mstp-clocks", compatible = "renesas,r8a7792-mstp-clocks",

1
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -412,7 +412,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&sdhi0 { &sdhi0 {

18
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -65,9 +65,8 @@
power-domains = <&sysc R8A7793_PD_CA15_CPU1>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
}; };
L2_CA15: cache-controller@0 { L2_CA15: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7793_PD_CA15_SCU>; power-domains = <&sysc R8A7793_PD_CA15_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
@ -109,6 +108,9 @@
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
}; };
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
@ -1179,10 +1181,12 @@
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>; clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7793_CLK_IRQC>; clock-indices = <
clock-output-names = "irqc"; R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS
>;
clock-output-names = "irqc", "intc-sys";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
@ -1426,11 +1430,11 @@
rcar_sound,dvc { rcar_sound,dvc {
dvc0: dvc-0 { dvc0: dvc-0 {
dmas = <&audma0 0xbc>; dmas = <&audma1 0xbc>;
dma-names = "tx"; dma-names = "tx";
}; };
dvc1: dvc-1 { dvc1: dvc-1 {
dmas = <&audma0 0xbe>; dmas = <&audma1 0xbe>;
dma-names = "tx"; dma-names = "tx";
}; };
}; };

1
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -375,7 +375,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&qspi { &qspi {

1
arch/arm/boot/dts/r8a7794-silk.dts
View File

@ -248,7 +248,6 @@
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&ether { &ether {

12
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -56,9 +56,8 @@
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
L2_CA7: cache-controller@0 { L2_CA7: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7794_PD_CA7_SCU>; power-domains = <&sysc R8A7794_PD_CA7_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
@ -75,6 +74,9 @@
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
}; };
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
@ -1248,10 +1250,10 @@
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>; clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7794_CLK_IRQC>; clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>;
clock-output-names = "irqc"; clock-output-names = "irqc", "intc-sys";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";

6
include/dt-bindings/clock/r7s72100-clock.h
View File

@ -49,7 +49,9 @@
#define R7S72100_CLK_SPI4 3 #define R7S72100_CLK_SPI4 3
/* MSTP12 */ /* MSTP12 */
#define R7S72100_CLK_SDHI0 3 #define R7S72100_CLK_SDHI00 3
#define R7S72100_CLK_SDHI1 2 #define R7S72100_CLK_SDHI01 2
#define R7S72100_CLK_SDHI10 1
#define R7S72100_CLK_SDHI11 0
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */

1
include/dt-bindings/clock/r8a73a4-clock.h
View File

@ -54,6 +54,7 @@
#define R8A73A4_CLK_IIC3 11 #define R8A73A4_CLK_IIC3 11
#define R8A73A4_CLK_IIC4 10 #define R8A73A4_CLK_IIC4 10
#define R8A73A4_CLK_IIC5 9 #define R8A73A4_CLK_IIC5 9
#define R8A73A4_CLK_INTC_SYS 8
#define R8A73A4_CLK_IRQC 7 #define R8A73A4_CLK_IRQC 7
/* MSTP5 */ /* MSTP5 */

1
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -82,6 +82,7 @@
/* MSTP4 */ /* MSTP4 */
#define R8A7790_CLK_IRQC 7 #define R8A7790_CLK_IRQC 7
#define R8A7790_CLK_INTC_SYS 8
/* MSTP5 */ /* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1 1 #define R8A7790_CLK_AUDIO_DMAC1 1

1
include/dt-bindings/clock/r8a7791-clock.h
View File

@ -72,6 +72,7 @@
/* MSTP4 */ /* MSTP4 */
#define R8A7791_CLK_IRQC 7 #define R8A7791_CLK_IRQC 7
#define R8A7791_CLK_INTC_SYS 8
/* MSTP5 */ /* MSTP5 */
#define R8A7791_CLK_AUDIO_DMAC1 1 #define R8A7791_CLK_AUDIO_DMAC1 1

1
include/dt-bindings/clock/r8a7792-clock.h
View File

@ -45,6 +45,7 @@
/* MSTP4 */ /* MSTP4 */
#define R8A7792_CLK_IRQC 7 #define R8A7792_CLK_IRQC 7
#define R8A7792_CLK_INTC_SYS 8
/* MSTP5 */ /* MSTP5 */
#define R8A7792_CLK_AUDIO_DMAC0 2 #define R8A7792_CLK_AUDIO_DMAC0 2

5
include/dt-bindings/clock/r8a7793-clock.h
View File

@ -77,10 +77,11 @@
/* MSTP4 */ /* MSTP4 */
#define R8A7793_CLK_IRQC 7 #define R8A7793_CLK_IRQC 7
#define R8A7793_CLK_INTC_SYS 8
/* MSTP5 */ /* MSTP5 */
#define R8A7793_CLK_AUDIO_DMAC1 1 #define R8A7793_CLK_AUDIO_DMAC1 1
#define R8A7793_CLK_AUDIO_DMAC0 2 #define R8A7793_CLK_AUDIO_DMAC0 2
#define R8A7793_CLK_ADSP_MOD 6 #define R8A7793_CLK_ADSP_MOD 6
#define R8A7793_CLK_THERMAL 22 #define R8A7793_CLK_THERMAL 22
#define R8A7793_CLK_PWM 23 #define R8A7793_CLK_PWM 23

1
include/dt-bindings/clock/r8a7794-clock.h
View File

@ -64,6 +64,7 @@
/* MSTP4 */ /* MSTP4 */
#define R8A7794_CLK_IRQC 7 #define R8A7794_CLK_IRQC 7
#define R8A7794_CLK_INTC_SYS 8
/* MSTP5 */ /* MSTP5 */
#define R8A7794_CLK_AUDIO_DMAC0 2 #define R8A7794_CLK_AUDIO_DMAC0 2