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drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctx

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Matches newer RM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2016-04-19 11:10:38 +10:00
parent 4d3df19a8e
commit 87ac331e3f
15 changed files with 36 additions and 28 deletions
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2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
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@ -81,8 +81,6 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *);
void gk104_grctx_generate_unkn(struct gf100_gr *);
void gk104_grctx_generate_r418bb8(struct gf100_gr *);
void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *);
void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_pagepool(struct gf100_grctx *);

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View File

@ -942,15 +942,6 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
}
void
gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x120074);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
@ -983,7 +974,6 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000);
gf100_gr_icmd(gr, grctx->icmd);

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
View File

@ -52,8 +52,6 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
gf100_gr_wait_idle(gr);

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
View File

@ -985,8 +985,6 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
gf100_gr_icmd(gr, grctx->icmd);
nvkm_wr32(device, 0x404154, idle_timeout);
gf100_gr_mthd(gr, grctx->mthd);

11
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c
View File

@ -45,15 +45,6 @@ gm200_grctx_generate_tpcid(struct gf100_gr *gr)
}
}
static void
gm200_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x12006c);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
gm200_grctx_generate_405b60(struct gf100_gr *gr)
{
@ -113,8 +104,6 @@ gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gm200_grctx_generate_rop_active_fbps(gr);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nvkm_wr32(device, 0x4041c4, tmp);

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
View File

@ -62,7 +62,6 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -119,6 +119,7 @@ struct gf100_gr_func {
void (*dtor)(struct gf100_gr *);
int (*init)(struct gf100_gr *);
void (*init_gpc_mmu)(struct gf100_gr *);
void (*init_rop_active_fbps)(struct gf100_gr *);
void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio;
struct {
@ -137,6 +138,7 @@ int gf100_gr_init(struct gf100_gr *);
int gf100_gr_rops(struct gf100_gr *);
int gk104_gr_init(struct gf100_gr *);
void gk104_gr_init_rop_active_fbps(struct gf100_gr *);
int gk20a_gr_init(struct gf100_gr *);

12
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -179,6 +179,15 @@ gk104_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
void
gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x120074);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
int
gk104_gr_init(struct gf100_gr *gr)
{
@ -230,6 +239,8 @@ gk104_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
gr->func->init_rop_active_fbps(gr);
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400100, 0xffffffff);
@ -312,6 +323,7 @@ gk104_gr_gpccs_ucode = {
static const struct gf100_gr_func
gk104_gr = {
.init = gk104_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.mmio = gk104_gr_pack_mmio,
.fecs.ucode = &gk104_gr_fecs_ucode,
.gpccs.ucode = &gk104_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View File

@ -183,6 +183,7 @@ gk110_gr_gpccs_ucode = {
static const struct gf100_gr_func
gk110_gr = {
.init = gk104_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.mmio = gk110_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,
.gpccs.ucode = &gk110_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View File

@ -103,6 +103,7 @@ gk110b_gr_pack_mmio[] = {
static const struct gf100_gr_func
gk110b_gr = {
.init = gk104_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.mmio = gk110b_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,
.gpccs.ucode = &gk110_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View File

@ -162,6 +162,7 @@ gk208_gr_gpccs_ucode = {
static const struct gf100_gr_func
gk208_gr = {
.init = gk104_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.mmio = gk208_gr_pack_mmio,
.fecs.ucode = &gk208_gr_fecs_ucode,
.gpccs.ucode = &gk208_gr_gpccs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View File

@ -272,6 +272,8 @@ gk20a_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
gr->func->init_rop_active_fbps(gr);
/* Enable FIFO access */
nvkm_wr32(device, 0x400500, 0x00010001);
@ -309,6 +311,7 @@ gk20a_gr_init(struct gf100_gr *gr)
static const struct gf100_gr_func
gk20a_gr = {
.init = gk20a_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
.rops = gf100_gr_rops,
.ppc_nr = 1,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -358,6 +358,8 @@ gm107_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
gr->func->init_rop_active_fbps(gr);
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400100, 0xffffffff);
@ -440,6 +442,7 @@ gm107_gr_gpccs_ucode = {
static const struct gf100_gr_func
gm107_gr = {
.init = gm107_gr_init,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.mmio = gm107_gr_pack_mmio,
.fecs.ucode = &gm107_gr_fecs_ucode,
.gpccs.ucode = &gm107_gr_gpccs_ucode,

12
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -52,6 +52,15 @@ gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
}
static void
gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x12006c);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
int
gm200_gr_init(struct gf100_gr *gr)
{
@ -98,6 +107,8 @@ gm200_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
gr->func->init_rop_active_fbps(gr);
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
@ -199,6 +210,7 @@ static const struct gf100_gr_func
gm200_gr = {
.init = gm200_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
.rops = gm200_gr_rops,
.ppc_nr = 2,
.grctx = &gm200_grctx,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
View File

@ -66,6 +66,7 @@ static const struct gf100_gr_func
gm20b_gr = {
.init = gk20a_gr_init,
.init_gpc_mmu = gm20b_gr_init_gpc_mmu,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
.rops = gm200_gr_rops,
.ppc_nr = 1,