Merge branch 'DP83869-WoL-and-Speed-optimization'
Dan Murphy says: ==================== DP83869 WoL and Speed optimization Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
8744c0a894
@ -4,12 +4,14 @@
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*/
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#include <linux/ethtool.h>
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/bitfield.h>
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#include <dt-bindings/net/ti-dp83869.h>
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@ -19,6 +21,7 @@
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#define MII_DP83869_PHYCTRL 0x10
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#define MII_DP83869_MICR 0x12
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#define MII_DP83869_ISR 0x13
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#define DP83869_CFG2 0x14
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#define DP83869_CTRL 0x1f
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#define DP83869_CFG4 0x1e
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@ -27,6 +30,13 @@
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#define DP83869_RGMIICTL 0x0032
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#define DP83869_STRAP_STS1 0x006e
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#define DP83869_RGMIIDCTL 0x0086
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#define DP83869_RXFCFG 0x0134
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#define DP83869_RXFPMD1 0x0136
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#define DP83869_RXFPMD2 0x0137
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#define DP83869_RXFPMD3 0x0138
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#define DP83869_RXFSOP1 0x0139
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#define DP83869_RXFSOP2 0x013A
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#define DP83869_RXFSOP3 0x013B
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#define DP83869_IO_MUX_CFG 0x0170
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#define DP83869_OP_MODE 0x01df
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#define DP83869_FX_CTRL 0x0c00
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@ -104,6 +114,26 @@
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#define DP83869_OP_MODE_MII BIT(5)
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#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
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/* RXFCFG bits*/
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#define DP83869_WOL_MAGIC_EN BIT(0)
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#define DP83869_WOL_PATTERN_EN BIT(1)
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#define DP83869_WOL_BCAST_EN BIT(2)
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#define DP83869_WOL_UCAST_EN BIT(4)
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#define DP83869_WOL_SEC_EN BIT(5)
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#define DP83869_WOL_ENH_MAC BIT(7)
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/* CFG2 bits */
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#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
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#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
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#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
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#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
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#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
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#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
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#define DP83869_DOWNSHIFT_1_COUNT 1
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#define DP83869_DOWNSHIFT_2_COUNT 2
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#define DP83869_DOWNSHIFT_4_COUNT 4
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#define DP83869_DOWNSHIFT_8_COUNT 8
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enum {
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DP83869_PORT_MIRRORING_KEEP,
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DP83869_PORT_MIRRORING_EN,
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@ -177,6 +207,256 @@ static int dp83869_config_intr(struct phy_device *phydev)
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return phy_write(phydev, MII_DP83869_MICR, micr_status);
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}
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static int dp83869_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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int val_rxcfg, val_micr;
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u8 *mac;
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int ret;
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val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
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if (val_rxcfg < 0)
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return val_rxcfg;
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val_micr = phy_read(phydev, MII_DP83869_MICR);
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if (val_micr < 0)
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return val_micr;
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
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WAKE_BCAST)) {
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val_rxcfg |= DP83869_WOL_ENH_MAC;
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val_micr |= MII_DP83869_MICR_WOL_INT_EN;
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if (wol->wolopts & WAKE_MAGIC ||
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wol->wolopts & WAKE_MAGICSECURE) {
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mac = (u8 *)ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFPMD1,
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mac[1] << 8 | mac[0]);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFPMD2,
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mac[3] << 8 | mac[2]);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFPMD3,
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mac[5] << 8 | mac[4]);
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if (ret)
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return ret;
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val_rxcfg |= DP83869_WOL_MAGIC_EN;
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} else {
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val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
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}
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if (wol->wolopts & WAKE_MAGICSECURE) {
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP2,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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if (ret)
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return ret;
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val_rxcfg |= DP83869_WOL_SEC_EN;
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} else {
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val_rxcfg &= ~DP83869_WOL_SEC_EN;
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}
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if (wol->wolopts & WAKE_UCAST)
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val_rxcfg |= DP83869_WOL_UCAST_EN;
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else
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val_rxcfg &= ~DP83869_WOL_UCAST_EN;
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if (wol->wolopts & WAKE_BCAST)
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val_rxcfg |= DP83869_WOL_BCAST_EN;
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else
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val_rxcfg &= ~DP83869_WOL_BCAST_EN;
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} else {
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val_rxcfg &= ~DP83869_WOL_ENH_MAC;
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val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
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}
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
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if (ret)
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return ret;
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return phy_write(phydev, MII_DP83869_MICR, val_micr);
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}
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static void dp83869_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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u16 value, sopass_val;
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wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
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WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
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if (value < 0) {
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phydev_err(phydev, "Failed to read RX CFG\n");
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return;
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}
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if (value & DP83869_WOL_UCAST_EN)
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wol->wolopts |= WAKE_UCAST;
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if (value & DP83869_WOL_BCAST_EN)
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wol->wolopts |= WAKE_BCAST;
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if (value & DP83869_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83869_WOL_SEC_EN) {
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sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP1);
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if (sopass_val < 0) {
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phydev_err(phydev, "Failed to read RX SOP 1\n");
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return;
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}
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP2);
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if (sopass_val < 0) {
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phydev_err(phydev, "Failed to read RX SOP 2\n");
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return;
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}
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
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DP83869_RXFSOP3);
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if (sopass_val < 0) {
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phydev_err(phydev, "Failed to read RX SOP 3\n");
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return;
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}
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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wol->wolopts |= WAKE_MAGICSECURE;
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}
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if (!(value & DP83869_WOL_ENH_MAC))
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wol->wolopts = 0;
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}
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static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
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{
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int val, cnt, enable, count;
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val = phy_read(phydev, DP83869_CFG2);
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if (val < 0)
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return val;
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enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
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cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
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switch (cnt) {
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case DP83869_DOWNSHIFT_1_COUNT_VAL:
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count = DP83869_DOWNSHIFT_1_COUNT;
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break;
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case DP83869_DOWNSHIFT_2_COUNT_VAL:
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count = DP83869_DOWNSHIFT_2_COUNT;
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break;
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case DP83869_DOWNSHIFT_4_COUNT_VAL:
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count = DP83869_DOWNSHIFT_4_COUNT;
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break;
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case DP83869_DOWNSHIFT_8_COUNT_VAL:
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count = DP83869_DOWNSHIFT_8_COUNT;
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break;
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default:
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return -EINVAL;
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}
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*data = enable ? count : DOWNSHIFT_DEV_DISABLE;
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return 0;
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}
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static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
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{
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int val, count;
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if (cnt > DP83869_DOWNSHIFT_8_COUNT)
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return -EINVAL;
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if (!cnt)
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return phy_clear_bits(phydev, DP83869_CFG2,
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DP83869_DOWNSHIFT_EN);
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switch (cnt) {
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case DP83869_DOWNSHIFT_1_COUNT:
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count = DP83869_DOWNSHIFT_1_COUNT_VAL;
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break;
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case DP83869_DOWNSHIFT_2_COUNT:
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count = DP83869_DOWNSHIFT_2_COUNT_VAL;
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break;
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case DP83869_DOWNSHIFT_4_COUNT:
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count = DP83869_DOWNSHIFT_4_COUNT_VAL;
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break;
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case DP83869_DOWNSHIFT_8_COUNT:
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count = DP83869_DOWNSHIFT_8_COUNT_VAL;
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break;
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default:
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phydev_err(phydev,
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"Downshift count must be 1, 2, 4 or 8\n");
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return -EINVAL;
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}
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val = DP83869_DOWNSHIFT_EN;
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val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
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return phy_modify(phydev, DP83869_CFG2,
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DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
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val);
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}
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static int dp83869_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return dp83869_get_downshift(phydev, data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int dp83869_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, const void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return dp83869_set_downshift(phydev, *(const u8 *)data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int dp83869_config_port_mirroring(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 = phydev->priv;
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@ -469,6 +749,12 @@ static int dp83869_config_init(struct phy_device *phydev)
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struct dp83869_private *dp83869 = phydev->priv;
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int ret, val;
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/* Force speed optimization for the PHY even if it strapped */
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ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
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DP83869_DOWNSHIFT_EN);
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if (ret)
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return ret;
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ret = dp83869_configure_mode(phydev, dp83869);
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if (ret)
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return ret;
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@ -568,6 +854,12 @@ static struct phy_driver dp83869_driver[] = {
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.config_intr = dp83869_config_intr,
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.read_status = dp83869_read_status,
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.get_tunable = dp83869_get_tunable,
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.set_tunable = dp83869_set_tunable,
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.get_wol = dp83869_get_wol,
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.set_wol = dp83869_set_wol,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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