forked from Minki/linux
Staging: comedi: fix style for multi-line comments in cb_pcidas64.c
This patch reformat multi-line comments which are not properly written according to the kernel coding style in cb_pcidas64.c Signed-off-by: Amaury Denoyelle <amaury.denoyelle@gmail.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Amaury Denoyelle
Greg Kroah-Hartman
parent
f51ff7e406
commit
85c12b82c6
@ -155,8 +155,10 @@ static inline unsigned int dac_msb_4020_reg(unsigned int channel)
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}
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enum read_only_registers {
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/* hardware status register,
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* reading this apparently clears pending interrupts as well */
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/*
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* hardware status register,
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* reading this apparently clears pending interrupts as well
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*/
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HW_STATUS_REG = 0x0,
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PIPE1_READ_REG = 0x4,
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ADC_READ_PNTR_REG = 0x8,
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@ -301,7 +303,8 @@ enum calibration_contents {
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CAL_GAIN_BIT = 0x800,
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};
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/* calibration sources for 6025 are:
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/*
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* calibration sources for 6025 are:
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* 0 : ground
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* 1 : 10V
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* 2 : 5V
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@ -661,8 +664,10 @@ static const struct hw_fifo_info ai_fifo_60xx = {
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.fifo_size_reg_mask = 0x7f,
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};
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/* maximum number of dma transfers we will chain together into a ring
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* (and the maximum number of dma buffers we maintain) */
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/*
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* maximum number of dma transfers we will chain together into a ring
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* (and the maximum number of dma buffers we maintain)
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*/
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#define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
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#define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
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#define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
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@ -1261,8 +1266,10 @@ static void enable_ai_interrupts(struct comedi_device *dev,
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bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
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EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
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/* Use pio transfer and interrupt on end of conversion
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* if CMDF_WAKE_EOS flag is set. */
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/*
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* Use pio transfer and interrupt on end of conversion
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* if CMDF_WAKE_EOS flag is set.
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*/
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if (cmd->flags & CMDF_WAKE_EOS) {
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/* 4020 doesn't support pio transfers except for fifo dregs */
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if (thisboard->layout != LAYOUT_4020)
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@ -1425,8 +1432,10 @@ static void init_stc_registers(struct comedi_device *dev)
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spin_lock_irqsave(&dev->spinlock, flags);
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/* bit should be set for 6025,
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* although docs say boards with <= 16 chans should be cleared XXX */
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/*
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* bit should be set for 6025,
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* although docs say boards with <= 16 chans should be cleared XXX
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*/
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if (1)
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devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
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writew(devpriv->adc_control1_bits,
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@ -1689,8 +1698,10 @@ static void i2c_write(struct comedi_device *dev, unsigned int address,
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uint8_t bitstream;
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static const int read_bit = 0x1;
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/* XXX need mutex to prevent simultaneous attempts to access
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* eeprom and i2c bus */
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/*
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* XXX need mutex to prevent simultaneous attempts to access
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* eeprom and i2c bus
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*/
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/* make sure we dont send anything to eeprom */
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devpriv->plx_control_bits &= ~CTL_EE_CS;
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@ -1782,14 +1793,18 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
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cal_en_bit = CAL_EN_60XX_BIT;
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else
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cal_en_bit = CAL_EN_64XX_BIT;
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/* select internal reference source to connect
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* to channel 0 */
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/*
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* select internal reference source to connect
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* to channel 0
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*/
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writew(cal_en_bit |
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adc_src_bits(devpriv->calibration_source),
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devpriv->main_iobase + CALIBRATION_REG);
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} else {
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/* make sure internal calibration source
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* is turned off */
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/*
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* make sure internal calibration source
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* is turned off
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*/
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writew(0, devpriv->main_iobase + CALIBRATION_REG);
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}
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/* load internal queue */
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@ -1821,8 +1836,10 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
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devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
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else
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devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
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/* update calibration/range i2c register only if necessary,
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* as it is very slow */
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/*
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* update calibration/range i2c register only if necessary,
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* as it is very slow
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*/
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if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
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uint8_t i2c_data = devpriv->i2c_cal_range_bits;
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@ -1830,10 +1847,12 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
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sizeof(i2c_data));
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}
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/* 4020 manual asks that sample interval register to be set
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/*
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* 4020 manual asks that sample interval register to be set
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* before writing to convert register.
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* Using somewhat arbitrary setting of 4 master clock ticks
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* = 0.1 usec */
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* = 0.1 usec
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*/
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writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
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writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
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}
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@ -1968,9 +1987,11 @@ static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
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return -EINVAL;
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}
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/* Gets nearest achievable timing given master clock speed, does not
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/*
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* Gets nearest achievable timing given master clock speed, does not
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* take into account possible minimum/maximum divisor values. Used
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* by other timing checking functions. */
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* by other timing checking functions.
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*/
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static unsigned int get_divisor(unsigned int ns, unsigned int flags)
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{
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unsigned int divisor;
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@ -1990,7 +2011,8 @@ static unsigned int get_divisor(unsigned int ns, unsigned int flags)
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return divisor;
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}
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/* utility function that rounds desired timing to an achievable time, and
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/*
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* utility function that rounds desired timing to an achievable time, and
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* sets cmd members appropriately.
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* adc paces conversions from master clock by dividing by (x + 3) where x is
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* 24 bit number
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@ -2474,8 +2496,10 @@ static int setup_channel_queue(struct comedi_device *dev,
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devpriv->main_iobase +
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ADC_QUEUE_FIFO_REG);
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}
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/* doing a queue clear is not specified in board docs,
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* but required for reliable operation */
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/*
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* doing a queue clear is not specified in board docs,
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* but required for reliable operation
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*/
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writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
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/* prime queue holding register */
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writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
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@ -2498,8 +2522,10 @@ static int setup_channel_queue(struct comedi_device *dev,
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devpriv->i2c_cal_range_bits &=
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~attenuate_bit(channel);
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}
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/* update calibration/range i2c register only if necessary,
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* as it is very slow */
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/*
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* update calibration/range i2c register only if necessary,
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* as it is very slow
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*/
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if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
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uint8_t i2c_data = devpriv->i2c_cal_range_bits;
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@ -2516,11 +2542,13 @@ static inline void load_first_dma_descriptor(struct comedi_device *dev,
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{
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struct pcidas64_private *devpriv = dev->private;
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/* The transfer size, pci address, and local address registers
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/*
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* The transfer size, pci address, and local address registers
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* are supposedly unused during chained dma,
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* but I have found that left over values from last operation
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* occasionally cause problems with transfer of first dma
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* block. Initializing them to zero seems to fix the problem. */
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* block. Initializing them to zero seems to fix the problem.
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*/
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if (dma_channel) {
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writel(0,
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devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
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@ -2675,15 +2703,19 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev)
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0x7fff;
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write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
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0x7fff;
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/* Get most significant bits (grey code).
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/*
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* Get most significant bits (grey code).
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* Different boards use different code so use a scheme
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* that doesn't depend on encoding. This read must
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* occur after reading least significant 15 bits to avoid race
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* with fifo switching to next segment. */
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* with fifo switching to next segment.
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*/
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prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
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/* if read and write pointers are not on the same fifo segment,
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* read to the end of the read segment */
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/*
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* if read and write pointers are not on the same fifo segment,
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* read to the end of the read segment
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*/
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read_segment = adc_upper_read_ptr_code(prepost_bits);
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write_segment = adc_upper_write_ptr_code(prepost_bits);
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@ -2712,7 +2744,8 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev)
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} while (read_segment != write_segment);
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}
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/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
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/*
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* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
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* pointers. The pci-4020 hardware only supports dma transfers (it only
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* supports the use of pio for draining the last remaining points from the
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* fifo when a data acquisition operation has completed).
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@ -2790,8 +2823,10 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
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devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
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ai_dma_ring_count(thisboard);
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}
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/* XXX check for dma ring buffer overrun
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* (use end-of-chain bit to mark last unused buffer) */
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/*
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* XXX check for dma ring buffer overrun
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* (use end-of-chain bit to mark last unused buffer)
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*/
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}
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static void handle_ai_interrupt(struct comedi_device *dev,
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@ -2939,8 +2974,10 @@ static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
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next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
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next_bits |= PLX_END_OF_CHAIN_BIT;
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devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
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/* clear end of chain bit on previous buffer now that we have set it
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* for the last buffer */
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/*
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* clear end of chain bit on previous buffer now that we have set it
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* for the last buffer
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*/
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next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
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next_bits &= ~PLX_END_OF_CHAIN_BIT;
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devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
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@ -3033,9 +3070,11 @@ static irqreturn_t handle_interrupt(int irq, void *d)
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plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
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status = readw(devpriv->main_iobase + HW_STATUS_REG);
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/* an interrupt before all the postconfig stuff gets done could
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/*
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* an interrupt before all the postconfig stuff gets done could
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* cause a NULL dereference if we continue through the
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* interrupt handler */
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* interrupt handler
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*/
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if (!dev->attached)
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return IRQ_HANDLED;
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@ -3195,8 +3234,10 @@ static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
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unsigned int nbytes;
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int i;
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/* clear queue pointer too, since external queue has
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* weird interactions with ao fifo */
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/*
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* clear queue pointer too, since external queue has
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* weird interactions with ao fifo
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*/
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writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
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writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
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@ -3465,7 +3506,8 @@ static int dio_60xx_wbits(struct comedi_device *dev,
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return insn->n;
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}
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/* pci-6025 8800 caldac:
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/*
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* pci-6025 8800 caldac:
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* address 0 == dac channel 0 offset
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* address 1 == dac channel 0 gain
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* address 2 == dac channel 1 offset
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@ -3475,7 +3517,8 @@ static int dio_60xx_wbits(struct comedi_device *dev,
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* address 6 == coarse adc gain
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* address 7 == fine adc gain
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*/
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/* pci-6402/16 uses all 8 channels for dac:
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/*
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* pci-6402/16 uses all 8 channels for dac:
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* address 0 == dac channel 0 fine gain
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* address 1 == dac channel 0 coarse gain
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* address 2 == dac channel 0 coarse offset
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@ -3484,7 +3527,7 @@ static int dio_60xx_wbits(struct comedi_device *dev,
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* address 5 == dac channel 1 coarse gain
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* address 6 == dac channel 0 fine offset
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* address 7 == dac channel 1 fine offset
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*/
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*/
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static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
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uint8_t value)
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@ -3744,7 +3787,8 @@ static int eeprom_read_insn(struct comedi_device *dev,
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return 1;
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}
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/* Allocate and initialize the subdevice structures.
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/*
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* Allocate and initialize the subdevice structures.
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*/
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static int setup_subdevices(struct comedi_device *dev)
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{
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@ -3779,8 +3823,10 @@ static int setup_subdevices(struct comedi_device *dev)
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s->cancel = ai_cancel;
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if (thisboard->layout == LAYOUT_4020) {
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uint8_t data;
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/* set adc to read from inputs
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* (not internal calibration sources) */
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/*
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* set adc to read from inputs
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* (not internal calibration sources)
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*/
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devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
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/* set channels to +-5 volt input ranges */
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for (i = 0; i < s->n_chan; i++)
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