forked from Minki/linux
tg3: Cleanup if codestyle
This patch cleans up the code style as it pertains to if statements. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
33f401aec7
commit
859a58879d
@ -1858,8 +1858,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
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/* Set Extended packet length bit for jumbo frames */
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
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}
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else {
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} else {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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@ -1977,8 +1976,7 @@ out:
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
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} else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
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if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
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@ -3466,11 +3464,10 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
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/* fallthru */
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case ANEG_STATE_RESTART:
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delta = ap->cur_time - ap->link_time;
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if (delta > ANEG_STATE_SETTLE_TIME) {
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if (delta > ANEG_STATE_SETTLE_TIME)
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ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
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} else {
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else
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ret = ANEG_TIMER_ENAB;
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}
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break;
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case ANEG_STATE_DISABLE_LINK_OK:
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@ -3494,9 +3491,8 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
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break;
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case ANEG_STATE_ABILITY_DETECT:
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if (ap->ability_match != 0 && ap->rxconfig != 0) {
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if (ap->ability_match != 0 && ap->rxconfig != 0)
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ap->state = ANEG_STATE_ACK_DETECT_INIT;
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}
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break;
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case ANEG_STATE_ACK_DETECT_INIT:
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@ -4174,9 +4170,9 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
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current_duplex = DUPLEX_FULL;
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else
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current_duplex = DUPLEX_HALF;
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}
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else
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} else {
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current_link_up = 0;
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}
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}
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}
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@ -4244,10 +4240,9 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
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}
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}
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}
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else if (netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE) &&
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(tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
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} else if (netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE) &&
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(tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
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u32 phy2;
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/* Select expansion interrupt status register */
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@ -4270,13 +4265,12 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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{
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int err;
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
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err = tg3_setup_fiber_phy(tp, force_reset);
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} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
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err = tg3_setup_fiber_mii_phy(tp, force_reset);
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} else {
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else
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err = tg3_setup_copper_phy(tp, force_reset);
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}
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
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u32 val, scale;
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@ -5560,9 +5554,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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tcp_hdr(skb)->check = 0;
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}
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else if (skb->ip_summed == CHECKSUM_PARTIAL)
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} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
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base_flags |= TXD_FLAG_TCPUDP_CSUM;
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}
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#if TG3_VLAN_TAG_USED
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if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
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base_flags |= (TXD_FLAG_VLAN |
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@ -5932,9 +5927,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
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if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
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tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
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ethtool_op_set_tso(dev, 0);
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}
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else
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} else {
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tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
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}
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} else {
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if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
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tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
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@ -7585,9 +7580,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
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if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
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if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
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tg3_abort_hw(tp, 1);
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}
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if (reset_phy)
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tg3_phy_reset(tp);
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@ -7740,8 +7734,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
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tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
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tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
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}
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else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
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} else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
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int fw_len;
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fw_len = tp->fw_len;
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@ -9424,9 +9417,8 @@ static inline u32 calc_crc(unsigned char *buf, int len)
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reg >>= 1;
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if (tmp) {
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if (tmp)
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reg ^= 0xedb88320;
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}
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}
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}
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@ -10380,8 +10372,7 @@ static int tg3_test_nvram(struct tg3 *tp)
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for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
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parity[k++] = buf8[i] & msk;
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i++;
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}
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else if (i == 16) {
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} else if (i == 16) {
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int l;
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u8 msk;
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@ -10844,9 +10835,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
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MII_TG3_EXT_CTRL_LNK3_LED_MODE);
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}
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tw32(MAC_MODE, mac_mode);
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}
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else
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} else {
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return -EINVAL;
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}
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err = -EIO;
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@ -12048,8 +12039,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
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ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
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}
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else {
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} else {
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u32 grc_mode;
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ret = tg3_nvram_lock(tp);
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@ -12069,8 +12059,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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ret = tg3_nvram_write_block_buffered(tp, offset, len,
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buf);
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}
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else {
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} else {
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ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
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buf);
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}
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@ -13119,8 +13108,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
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tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
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tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
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}
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else {
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} else {
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struct pci_dev *bridge = NULL;
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do {
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@ -14018,11 +14006,10 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
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}
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pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
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if (to_device) {
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if (to_device)
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tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
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} else {
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else
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tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
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}
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ret = -ENODEV;
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for (i = 0; i < 40; i++) {
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@ -14227,10 +14214,10 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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if (pci_dev_present(dma_wait_state_chipsets)) {
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tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
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tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
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}
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else
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} else {
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/* Safe to use the calculated DMA boundary. */
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tp->dma_rwctrl = saved_dma_rwctrl;
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}
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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}
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