forked from Minki/linux
ath9k_hw: Add AR9003 PHY support
This add stubs for PHY support for the AR9003 hardware family. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
db3cc53a2f
commit
8525f2801d
@ -14,6 +14,7 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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ath9k_hw-y:= hw.o \
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ar9003_phy.o \
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ar9002_phy.o \
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ar5008_phy.o \
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eeprom.o \
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147
drivers/net/wireless/ath/ath9k/ar9003_phy.c
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147
drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@ -0,0 +1,147 @@
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/*
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* Copyright (c) 2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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/**
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* ar9003_hw_set_channel - set channel on single-chip device
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* @ah: atheros hardware structure
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* @chan:
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*
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* This is the function to change channel on single-chip devices, that is
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* all devices after ar9280.
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*
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* This function takes the channel value in MHz and sets
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* hardware channel value. Assumes writes have been enabled to analog bus.
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*
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* Actual Expression,
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*
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* For 2GHz channel,
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* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*
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* For 5GHz channel,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
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* (freq_ref = 40MHz/(24>>amodeRefSel))
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*
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* For 5GHz channels which are 5MHz spaced,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*/
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static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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/* TODO */
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return 0;
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}
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/**
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* ar9003_hw_spur_mitigate - convert baseband spur frequency
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* @ah: atheros hardware structure
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* @chan:
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*
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* For single-chip solutions. Converts to baseband spur frequency given the
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* input channel frequency and compute register settings below.
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*
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* Spur mitigation for MRC CCK
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*/
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static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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}
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static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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return 0;
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}
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static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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}
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static void ar9003_hw_init_bb(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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}
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static int ar9003_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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return -1;
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}
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static void ar9003_hw_set_rfmode(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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}
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static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
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{
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/* TODO */
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}
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static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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}
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static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
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{
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/* TODO */
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return false;
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}
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static void ar9003_hw_rfbus_done(struct ath_hw *ah)
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{
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/* TODO */
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}
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static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
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{
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/* TODO */
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}
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static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
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{
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/* TODO */
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}
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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priv_ops->rf_set_freq = ar9003_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
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priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
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priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
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priv_ops->init_bb = ar9003_hw_init_bb;
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priv_ops->process_ini = ar9003_hw_process_ini;
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priv_ops->set_rfmode = ar9003_hw_set_rfmode;
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priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
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priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
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priv_ops->rfbus_req = ar9003_hw_rfbus_req;
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priv_ops->rfbus_done = ar9003_hw_rfbus_done;
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priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
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priv_ops->set_diversity = ar9003_hw_set_diversity;
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}
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@ -27,6 +27,7 @@
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#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
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static void ar9002_hw_attach_ops(struct ath_hw *ah);
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static void ar9003_hw_attach_ops(struct ath_hw *ah);
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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@ -858,6 +859,14 @@ static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
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"needs fixup for AR_AN_TOP2 register\n");
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}
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static void ath9k_hw_attach_ops(struct ath_hw *ah)
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{
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if (AR_SREV_9300_20_OR_LATER(ah))
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ar9003_hw_attach_ops(ah);
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else
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ar9002_hw_attach_ops(ah);
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}
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/* Called for all hardware families */
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static int __ath9k_hw_init(struct ath_hw *ah)
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{
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@ -873,7 +882,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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return -EIO;
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}
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ar9002_hw_attach_ops(ah);
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ath9k_hw_attach_ops(ah);
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if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
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ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
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@ -3524,8 +3533,13 @@ static void ar9002_hw_attach_ops(struct ath_hw *ah)
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ops->config_pci_powersave = ar9002_hw_configpcipowersave;
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ar5008_hw_attach_phy_ops(ah);
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if (AR_SREV_9280_10_OR_LATER(ah))
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ar9002_hw_attach_phy_ops(ah);
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else
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ar5008_hw_attach_phy_ops(ah);
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}
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/* Sets up the AR9003 hardware familiy callbacks */
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static void ar9003_hw_attach_ops(struct ath_hw *ah)
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{
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ar9003_hw_attach_phy_ops(ah);
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}
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@ -783,8 +783,9 @@ void ath9k_hw_htc_resetinit(struct ath_hw *ah);
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void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
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u32 *coef_mantissa, u32 *coef_exponent);
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void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
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void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
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#define ATH_PCIE_CAP_LINK_CTRL 0x70
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#define ATH_PCIE_CAP_LINK_L0S 1
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