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net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter

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Fix 32-bit variable shift wrapping in dr_ste_v1_get_miss_addr.

Fixes: a6098129c7 ("net/mlx5: DR, Add STEv1 setters and getters")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik 2021-02-06 22:11:52 +02:00 committed by Saeed Mahameed
parent dc694f11a7
commit 84076c4c80
1 changed files with 2 additions and 2 deletions
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4
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
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@ -264,8 +264,8 @@ static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)
static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)
{
u64 index =
(MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32) << 26);
((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32)) << 26);
return index << 6;
}