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mips: bmips: dts: add BCM6328 reset controller support

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BCM6328 SoCs have a reset controller for certain components.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Álvaro Fernández Rojas 2020-06-17 12:50:36 +02:00 committed by Thomas Bogendoerfer
parent aac025437f
commit 83f865d7e3
2 changed files with 24 additions and 0 deletions
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6
arch/mips/boot/dts/brcm/bcm6328.dtsi
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@ -57,6 +57,12 @@
#clock-cells = <1>; #clock-cells = <1>;
}; };
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 { periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc"; compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>, reg = <0x10000020 0x10>,

18
include/dt-bindings/reset/bcm6328-reset.h Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6328_H
#define __DT_BINDINGS_RESET_BCM6328_H
#define BCM6328_RST_SPI 0
#define BCM6328_RST_EPHY 1
#define BCM6328_RST_SAR 2
#define BCM6328_RST_ENETSW 3
#define BCM6328_RST_USBS 4
#define BCM6328_RST_USBH 5
#define BCM6328_RST_PCM 6
#define BCM6328_RST_PCIE_CORE 7
#define BCM6328_RST_PCIE 8
#define BCM6328_RST_PCIE_EXT 9
#define BCM6328_RST_PCIE_HARD 10
#endif /* __DT_BINDINGS_RESET_BCM6328_H */